Datasheet

2/S x I
RMS
(40 mW/50:)
LMH6672
www.ti.com SNOS957G –APRIL 2001–REVISED MARCH 2013
To maintain low distortion, in a Class AB output stage, an idle current, I
Q
, is maintained through the output
transistors when there is little or no output signal. In the LMH6672, about 4.8 mA of the total quiescent supply
current of 14.4 mA flows through the output stages.
Under normal large signal conditions, as the output voltage swings positive, one transistor of the output pair will
conduct the load current, while the other transistor shuts off, and dissipates no power. During the negative signal
swing this situation is reversed, with the lower transistor sinking the load current while the upper transistor is cut
off. The current in each transistor will approximate a half wave rectified version of the total load current.
Because the output stage idle current is now routed into the load, 4.8 mA can be subtracted from the quiescent
supply current when calculating the quiescent power when the output is driving a load.
The power dissipation caused by driving a load in a DSL application, using a 1:2 turns ratio transformer driving
20 mW into the subscriber line and 20 mW into the back termination resistors, can be calculated as follows:
P
DRIVER
= P
TOT
– (P
TERM
+ P
LINE
Where
• P
DRIVER
is the LMH6672 power dissipation
• P
TOT
is the total power drawn from the power supply
• P
TERM
is the power dissipated in the back termination resistors
• P
LINE
is the power sent into the subscriber line
• At full specified power, P
TERM
= P
LINE
= 20 mW, P
TOT
= V
S
× I
S
(1)
In this application, V
S
= 12V.
I
S
= I
Q
+ A
VG
|I
OUT
|.
I
Q
= the LMH6672 quiescent current minus the output stage idle current.
I
Q
= 14.4 – 4.8 = 9.6 mA
Average (A
VG
) |I
OUT
| for a full-rate ADSL CPE application, using a 1:2 turns ratio transformer, is = 28.28
mA RMS.
For a Gaussian signal, which the DMT ADSL signal approximates, A
VG
|I
OUT
| = = 22.6 mA. Therefore,
P
TOT
= (22.6 mA + 9.6 mA) × 12V = 386 mW and P
DRIVER
is 40 = 346 mW.
In the SOIC package, with a θ
JA
of 172°C/W, this causes a temperature rise of 60°C. With an ambient
temperature at the maximum recommended 85°C, the T
J
is at 145°C, well below the specified 150°C maximum.
Even if we assume the absolute maximum I
S
over temperature of 18 mA, when we scale up the I
Q
proportionally
to 7 mA, the P
DRIVER
only goes up by 41 mW causing a 62°C rise to 147°C.
Although very few CPE applications will ever operate in an environment as hot as 85°C, if a lower T
J
is desired
or the LMH6672 is to be used in an application where the power dissipation is higher, the SO PowerPAD (DDA)
package provides a much lower θ
JA
of only 58.6°C/W. Using the same P
DRIVER
as above, we find that the
temperature rise is only 19° and 21°C, resulting in T
J
's in an 85°C ambient of 104°C and 106°C respectively.
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