Datasheet

LMH6654, LMH6655
www.ti.com
SNOS956D JUNE 2001REVISED MARCH 2013
±5V Electrical Characteristics
Unless otherwise specified, all limits ensured for T
J
= 25°C, V
+
= +5V, V
= 5V, V
CM
= 0V, A
V
= +1, R
F
= 25 for gain = +1,
R
F
= 402Ω for gain = +2, and R
L
= 100Ω. Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min Typ Max Units
(1) (2) (1)
Dynamic Performance
A
V
= +1 250
A
V
= +2 130
f
CL
Close Loop Bandwidth MHz
A
V
= +5 52
A
V
= +10 26
Gain Bandwidth Product A
V
+5 260 MHz
GBWP
Bandwidth for 0.1 dB Flatness A
V
+1 18 MHz
φm Phase Margin 50 deg
SR Slew Rate
(3)
A
V
= +1, V
IN
= 2 V
PP
200 V/µs
Settling Time
25 ns
0.01%
t
S
A
V
= +1, 2V Step
0.1% 15 ns
t
r
Rise Time A
V
= +1, 0.2V Step 1.4 ns
t
f
Fall Time A
V
= +1, 0.2V Step 1.2 ns
Distortion and Noise Response
e
n
Input Referred Voltage Noise f 0.1 MHz 4.5 nV/Hz
i
n
Input-Referred Current Noise f 0.1 MHz 1.7 pA/Hz
Second Harmonic Distortion A
V
= +1, f = 5 MHz 80
dBc
Third Harmonic Distortion V
O
= 2 V
PP
, R
L
= 100 85
Input Referred, 5 MHz, 80 dB
X
t
Crosstalk (for LMH6655 only)
Channel-to-Channel
DG Differential Gain A
V
= +2, NTSC, R
L
= 150 0.01 %
DP Differential Phase A
V
= +2, NTSC, R
L
= 150 0.025 deg
Input Characteristics
3 ±1 3
V
OS
Input Offset Voltage V
CM
= 0V mV
4 4
TC V
OS
Input Offset Average Drift V
CM
= 0V
(4)
6 µV/°C
5 12
I
B
Input Bias Current V
CM
= 0V µA
18
1 0.3 1
I
OS
Input Offset Current V
CM
= 0V µA
2 2
Common Mode 4 M
R
IN
Input Resistance
Differential Mode 20 k
Common Mode 1.8
C
IN
Input Capacitance pF
Differential Mode 1
Input Referred, 70 90
CMRR Common Mode Rejection Ration dB
V
CM
= 0V to 5V 68
5.15 5.0
CMVR Input Common- Mode Voltage Range CMRR 50 dB V
3.5 3.7
Transfer Characteristics
V
O
= 4 V
PP
, R
L
= 100 60 67
A
VOL
Large Signal Voltage Gain dB
58
(1) All limits are specified by testing or statistical analysis.
(2) Typical Values represent the most likely parametric norm.
(3) Slew rate is the slower of the rising and falling slew rates. Slew rate is rate of change from 10% to 90% of output voltage step.
(4) Offset voltage average drift is determined by dividing the change in V
OS
at temperature extremes into the total temperature change.
Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LMH6654 LMH6655