Datasheet

LMH6642, LMH6643, LMH6644
www.ti.com
SNOS966P MAY 2001REVISED MARCH 2013
Operating Ratings
(1)
Supply Voltage (V
+
– V
) 2.7V to 12.8V
Junction Temperature Range
(2)
40°C to +85°C
Package Thermal Resistance
(2)
(θ
JA
) 5-Pin SOT-23 265°C/W
8-Pin SOIC 190°C/W
8-Pin VSSOP 235°C/W
14-Pin SOIC 145°C/W
14- Pin TSSOP 155°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical Characteristics.
(2) The maximum power dissipation is a function of T
J(MAX)
, θ
JA
, and T
A
. The maximum allowable power dissipation at any ambient
temperature is P
D
= (T
J(MAX)
- T
A
)/ θ
JA
. All numbers apply for packages soldered directly onto a PC board.
3V Electrical Characteristics
Unless otherwise specified, all limits guaranteed for at T
J
= 25°C, V
+
= 3V, V
= 0V, V
CM
= V
O
= V
+
/2, V
ID
(input differential
voltage) as noted (where applicable) and R
L
= 2k to V
+
/2. Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min Typ Max Units
(1) (2) (1)
BW 3dB BW A
V
= +1, V
OUT
= 200mV
PP
80 115
MHz
A
V
= +2, 1, V
OUT
= 200mV
PP
46
BW
0.1dB
0.1dB Gain Flatness A
V
= +2, R
L
= 150 to V+/2, 19 MHz
R
L
= 402, V
OUT
= 200mV
PP
PBW Full Power Bandwidth A
V
= +1, 1dB, V
OUT
= 1V
PP
40 MHz
e
n
Input-Referred Voltage Noise f = 100kHz 17
nV/Hz
f = 1kHz 48
i
n
Input-Referred Current Noise f = 100kHz 0.90
pA/Hz
f = 1kHz 3.3
THD Total Harmonic Distortion f = 5MHz, V
O
= 2V
PP
, A
V
= 1, 48
dBc
R
L
= 100 to V
+
/2
DG Differential Gain V
CM
= 1V, NTSC, A
V
= +2 0.17
R
L
=150 to V
+
/2
%
R
L
=1k to V
+
/2 0.03
DP Differential Phase V
CM
= 1V, NTSC, A
V
= +2 0.05
R
L
=150 to V
+
/2
deg
R
L
=1k to V
+
/2 0.03
CT Rej. Cross-Talk Rejection f = 5MHz, Receiver: 47 dB
R
f
= R
g
= 510, A
V
= +2
T
S
Settling Time V
O
= 2V
PP
, ±0.1%, 8pF Load, 68 ns
V
S
= 5V
SR Slew Rate
(3)
A
V
= 1, V
I
= 2V
PP
90 120 V/µs
V
OS
Input Offset Voltage For LMH6642 and LMH6644 ±1 ±5
±7
mV
For LMH6643 ±1 ±3.4
±7
TC V
OS
Input Offset Average Drift See
(4)
±5 µV/°C
I
B
Input Bias Current See
(5)
1.50 2.60
µA
3.25
I
OS
Input Offset Current 20 800
nA
1000
R
IN
Common Mode Input Resistance 3 M
(1) All limits are guaranteed by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm.
(3) Slew rate is the average of the rising and falling slew rates.
(4) Offset voltage average drift determined by dividing the change in V
OS
at temperature extremes by the total temperature change.
(5) Positive current corresponds to current flowing into the device.
Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LMH6642 LMH6643 LMH6644