Datasheet

200 mV/DIV 20 ns/DIV
+
-
V
bias
C
d
10
-
200pF
Photodiode
R
d
C1
100nF
Q1
2N3904
R5
510:
R2
1.8k:
D1
1N4148
R3
1k:
R11
910
:
R10
1k:
-1mA
PP
C
f
5pF
R
f
1k:
V
CC
=
+5V
R
bias
Photodiode
Equivalent
Circuit
I
d
×
100k:
V
out
+5V
x
SQRT
GBWP/(2SR
F
˜C
IN
)
f
P
=
C
F
=

SQRT
(C
IN
)/(2S˜GBWP ˜R
F
)
LMH6642, LMH6643, LMH6644
www.ti.com SNOS966P –MAY 2001–REVISED MARCH 2013
No matter how low an R
f
is selected, there is a need for C
f
in order to stabilize the circuit. The reason for this is
that the Op Amp input capacitance and Q1 equivalent collector capacitance together (C
IN
) will cause additional
phase shift to the signal fed back to the inverting node. C
f
will function as a zero in the feedback path counter-
acting the effect of the C
IN
and acting to stabilized the circuit. By proper selection of C
f
such that the Op Amp
open loop gain is equal to the inverse of the feedback factor at that frequency, the response is optimized with a
theoretical 45° phase margin.
(1)
where GBWP is the Gain Bandwidth Product of the Op Amp
Optimized as such, the I-V converter will have a theoretical pole, f
p
, at:
(2)
With Op Amp input capacitance of 3pF and an estimate for Q1 output capacitance of about 3pF as well, C
IN
=
6pF. From the typical performance plots, LMH6642/6643 family GBWP is approximately 57MHz. Therefore, with
R
f
= 1k, from Equation 1 and Equation 2 above.
C
f
= ∼4.1pF and f
p
= 39MHz
Figure 63. Single Supply Photodiode I-V Converter
For this example, optimum C
f
was empirically determined to be around 5pF. This time domain response is shown
in Figure 64 below showing about 9ns rise/fall times, corresponding to about 39MHz for f
p
. The overall supply
current from the +5V supply is around 5mA with no load.
Figure 64. Converter Step Response (1V
PP
, 20 ns/DIV)
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