Datasheet

V
noise
#
@ > @ > @
RtHznVRtHznVRtHznV 10/88.02.5/82.12.6/69
2
2
2
3
2
x+x+x
>
.0 RtHznV/4.23=
V
noise
#
>
@
> @ > @
2
_
2
2
_
3
2
))(2.)2/)(2.
)2/1(
KeKe
Ke
thermalRg
thermalRin
n
++
+
LMH6629
www.ti.com SNOSB18G –APRIL 2010–REVISED MARCH 2013
Equation 14: Converter Noise Expression (14)
e
n
is the LMH6629 input noise voltage and e
Rin_thermal
is the thermal noise of R
IN
. The “2
3
” and the “2
2
” multipliers
account for the different instances of each noise source (2 for e
n
, and 1 for e
Rin_thermal
).
Equation 14 evaluated for the circuit example of Figure 71 is shown below:
Equation 15: Converter Noise Expression Evaluated (15)
Because of the LMH6629’s low input noise voltage (e
n
), noise is dominated by the thermal noise of R
IN
. It is
evident that the input resistor, R
IN
, can be reduced to lower the noise with lower input impedance as the trade-
off.
LAYOUT CONSIDERATIONS
Texas Instruments offers evaluation board(s) to aid in device testing and characterization and as a guide for
proper layout. As is the case with all high-speed amplifiers, accepted-practice RF design technique on the PCB
layout is mandatory. Generally, a good high-frequency layout exhibits a separation of power supply and ground
traces from the inverting input and output pins. Parasitic capacitances between these nodes and ground may
cause frequency response peaking and possible circuit oscillations (see Application Note OA-15 for more
information). Use high-quality chip capacitors with values in the range of 1000 pF to 0.1F for power supply
bypassing. One terminal of each chip capacitor is connected to the ground plane and the other terminal is
connected to a point that is as close as possible to each supply pin as allowed by the manufacturer’s design
rules. In addition, connect a tantalum capacitor with a value between 4.7 μF and 10 μF in parallel with the chip
capacitor.
Harmonic Distortion, especially HD2, is strongly influenced by the layout and in particular can be affected by
decoupling capacitors placed between the V
+
and V
-
terminals as close to the device leads as possible.
Signal lines connecting the feedback and gain resistors should be as short as possible to minimize inductance
and microstrip line effect. Place input and output termination resistors as close as possible to the input/output
pins. Traces greater than 1 inch in length should be impedance matched to the corresponding load termination.
Symmetry between the positive and negative paths in the layout of differential circuitry should be maintained to
minimize the imbalance of amplitude and phase of the differential signal.
Component value selection is another important parameter in working with high-speed / high-performance
amplifiers. Choosing external resistors that are large in value compared to the value of other critical components
will affect the closed loop behavior of the stage because of the interaction of these resistors with parasitic
capacitances. These parasitic capacitors could either be inherent to the device or be a by-product of the board
layout and component placement. Moreover, a large resistor will also add more thermal noise to the signal path.
Either way, keeping the resistor values low will diminish this interaction. On the other hand, choosing very low
value resistors could load down nodes and will contribute to higher overall power dissipation and high distortion.
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