Datasheet

LMH6601, LMH6601-Q1
SNOSAK9E –JUNE 2006–REVISED MARCH 2013 www.ti.com
2.7V ELECTRICAL CHARACTERISTICS (continued)
Single Supply with V
S
= 2.7V, A
V
= +2, R
F
= 604Ω, SD tied to V
+
, V
OUT
= V
S
/2, R
L
= 150Ω to V
−
unless otherwise specified.
Boldface limits apply at temperature extremes.
(1)
Symbol Parameter Condition Min
(2)
Typ
(2)
Max
(2)
Units
−PSRR Negative Power Supply Rejection DC 56 69
dB
Ratio 53
CMRR Common Mode Rejection Ratio DC 57 77 dB
52
CMVR Input Voltage Range CMRR > 50 dB V
−
-0.20 – V
+
-1.5 V
I
CC
Supply Current Normal Operation 9.0 10.6
mA
V
OUT
= V
S
/2 12.5
Shutdown 100 nA
SD tied to ≤ 0.27V
(5)
VOH1 Output High Voltage R
L
= 150Ω to V
–
–260 –200
(Relative to V
+
) –420
VOH2 R
L
= 75Ω to V
S
/2 –200 mV
VOH3 R
L
= 10 kΩ to V
–
–50 –10
100
VOL1 Output Low Voltage R
L
= 150Ω to V
–
+4 +45
(Relative to V
–
) +125
VOL2 R
L
= 75Ω to V
S
/2 +125 mV
VOL3 R
L
= 10 kΩ to V
–
+4 +45
125
I
O
Output Current V
OUT
≤ 0.6V from Respective Source 25
Supply
Sink 62
mA
I
O
_1 V
OUT
= V
S
/2, V
ID
= ±18 mV Source 25
(6)
Sink 35
Load Output Load Rating THD < −30 dBc, f = 200 kHz, R
L
tied to 40 Ω
V
S
/2, V
OUT
= 2.2 V
PP
R
O
_Enable Output Resistance Enabled, A
V
= +1 0.2 Ω
R
O
_Disabled Output Resistance Shutdown >100 MΩ
C
O
_Disabled Output Capacitance Shutdown 5.6 pF
Miscellaneous Performance
VDMAX Voltage Limit for Disable (Pin 5) See
(5)
0 0.27 V
VDMIN Voltage Limit for Enable (Pin 5) See
(5)
2.43 2.7 V
I
i
Logic Input Current (Pin 5) SD = 2.7V
(5)
4 pA
V
_glitch
Turn-on Glitch 1.2 V
T
on
Turn-on Time 5.2 µs
T
off
Turn-off Time 760 ns
Isolation
OFF
Off Isolation 1 MHz, R
L
= 1 kΩ 60 dB
(5) SD logic is CMOS compatible. To ensure proper logic level and to minimize power supply current, SD should typically be less than 10%
of total supply voltage away from either supply rail.
(6) “V
ID
” is input differential voltage (input overdrive).
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