Datasheet

LMH6601, LMH6601-Q1
SNOSAK9E –JUNE 2006–REVISED MARCH 2013 www.ti.com
3.3V ELECTRICAL CHARACTERISTICS (continued)
Single Supply with V
S
= 3.3V, A
V
= +2, R
F
= 604Ω, SD tied to V
+
, V
OUT
= V
S
/2, R
L
= 150Ω to V
−
unless otherwise specified.
Boldface limits apply at temperature extremes.
(1)
Symbol Parameter Condition Min
(2)
Typ
(2)
Max
(2)
Units
I
B
Input Bias Current See
(4)
5 50 pA
I
OS
Input Offset Current See
(4)
2 25 pA
R
IN
Input Resistance 0V ≤ V
IN
≤ 1.8V 15 TΩ
C
IN
Input Capacitance 1.4 pF
+PSRR Positive Power Supply Rejection DC 61 80 dB
Ratio 51
−PSRR Negative Power Supply Rejection DC 57 72 dB
Ratio 52
CMRR Common Mode Rejection Ratio DC 58 73 dB
55
CMVR Input Voltage Range CMRR > 50 dB V
−
-0.20 – V
+
-1.5 V
I
CC
Supply Current Normal Operation 9.2 11
mA
V
OUT
= V
S
/2 13
Shutdown 100 nA
SD tied to ≤ 0.33V
(5)
VOH1 Output High Voltage R
L
= 150Ω to V
–
–210 –190
(Relative to V
+
) –360
VOH2 R
L
= 75Ω to V
S
/2 –190 mV
VOH3 R
L
= 10 kΩ to V
−
–50 –10
–100
VOL1 Output Low Voltage R
L
= 150Ω to V
–
+4 +45
(Relative to V
–
) +125
VOL2 R
L
= 75Ω to V
S
/2 +105 mV
VOL3 R
L
= 10 kΩ to V
–
+4 +45
+125
I
O
Output Current V
OUT
< 0.6V from Respective Source 50
Supply
Sink 75 mA
I
O
_1 V
OUT
= V
S
/2, V
ID
= ±18 mV
(6)
±75
Load Output Load Rating THD < −30 dBc, f = 200 kHz, 25 Ω
R
L
tied to V
S
/2, V
OUT
= 2.6 V
PP
R
O
_Enabled Output Resistance Enabled, A
V
= +1 0.2 Ω
R
O
_Disabled Output Resistance Shutdown >100 MΩ
C
O
_Disabled Output Capacitance Shutdown 5.6 pF
Miscellaneous Performance
VDMAX Voltage Limit for Disable (Pin 5) See
(5)
0 0.33 V
VDMIN Voltage Limit for Enable (Pin 5) See
(5)
2.97 3.3 V
I
i
Logic Input Current (Pin 5) SD = 3.3V
(5)
8 pA
V
_glitch
Turn-on Glitch 1.6 V
T
on
Turn-on Time 3.5 µs
T
off
Turn-off Time 500 ns
Isolation
OFF
Off Isolation 1 MHz, R
L
= 1 kΩ 60 dB
(4) This parameter is ensured by design and/or characterization and is not tested in production.
(5) SD logic is CMOS compatible. To ensure proper logic level and to minimize power supply current, SD should typically be less than 10%
of total supply voltage away from either supply rail.
(6) “V
ID
” is input differential voltage (input overdrive).
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