Datasheet
1
10 100 1000
FREQUENCY (MHz)
-10
-8
-6
-4
-2
0
2
NORMALIZED GAIN (dB)
C
L
= 100 pF, R
OUT
= 19:
V
OUT
= 1 V
PP
C
L
|| 1 k:
V
S
= ±5V
A
V
= 2 (V/V)
C
L
= 56 pF, R
OUT
= 24:
C
L
= 18 pF, R
OUT
= 48:
C
L
= 8.6 pF, R
OUT
= 63:
1
10 100 1000
CAPACTIVE LOAD (pF)
0
10
20
30
40
50
60
70
80
90
SUGGESTED R
OUT
(:)
V
S
= ±5V
LOAD = 1 k:|| C
L
LMH6574
R
OUT
45:
C
L
10 pF
R
L
1 k:
V
OUT
LMH6574
www.ti.com
SNCS103C –NOVEMBER 2004–REVISED SEPTEMBER 2005
Figure 33. Decoupling Capacitive Loads
Figure 34. Suggested R
OUT
vs. Capacitive Load
Figure 35. Frequency Response vs. Capacitive Load
LAYOUT CONSIDERATIONS
Whenever questions about layout arise, use the evaluation board as a guide. The LMH730276 is the evaluation
board supplied with samples of the LMH6574. To reduce parasitic capacitances, ground and power planes
should be removed near the input and output pins. For long signal paths controlled impedance lines should be
used, along with impedance matching elements at both ends. Bypass capacitors should be placed as close to
the device as possible. Bypass capacitors from each rail to ground are applied in pairs. The larger electrolytic
bypass capacitors can be located farther from the device, the smaller ceramic capacitors should be placed as
close to the device as possible. In Figure 28, the capacitor between V
+
and V
−
is optional, but is recommended
for best second harmonic distortion. Another way to enhance performance is to use pairs of 0.01 μF and 0.1 μF
ceramic capacitors for each supply bypass.
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