Datasheet

1
10 100 1000
FREQUENCY (MHz)
-10
-8
-6
-4
-2
0
2
NORMALIZED GAIN (dB)
C
L
= 100 pF, R
OUT
= 19:
V
OUT
= 1 V
PP
C
L
|| 1 k:
V
S
= ±5V
A
V
= 2 (V/V)
C
L
= 56 pF, R
OUT
= 24:
C
L
= 18 pF, R
OUT
= 48:
C
L
= 8.6 pF, R
OUT
= 63:
1
10 100 1000
CAPACTIVE LOAD (pF)
0
10
20
30
40
50
60
70
80
90
SUGGESTED R
OUT
(:)
V
S
= ±5V
LOAD = 1 k:|| C
L
LMH6570
SNCS104C –APRIL 2005–REVISED MAY 2013 www.ti.com
Figure 32. Suggested R
OUT
vs. Capacitive Load Figure 33. Frequency Response vs. Capacitive
Load
LAYOUT CONSIDERATIONS
To reduce parasitic capacitances, ground and power planes should be removed near the input and output pins.
For long signal paths controlled impedance lines should be used, along with impedance matching elements at
both ends. Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each
rail to ground are applied in pairs. The larger electrolytic bypass capacitors can be located farther from the
device, the smaller ceramic capacitors should be placed as close to the device as possible. In Figure 26, the
capacitor between V
+
and V
−
is optional, but is recommended for best second harmonic distortion. Another way
to enhance performance is to use pairs of 0.01μF and 0.1μF ceramic capacitors for each supply bypass.
POWER DISSIPATION
The LMH6570 is optimized for maximum speed and performance in the small form factor of the standard SOIC
package. To ensure maximum output drive and highest performance, thermal shutdown is not provided.
Therefore, it is of utmost importance to make sure that the T
JMAX
is never exceeded due to the overall power
dissipation.
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