Datasheet

INPUT FREQUENCY (MHz)
(dB)
100
95
90
85
80
75
70
65
60
55
50
0 5 10 15 20 25 30 35 40
SFDR (dBc)
SNR (dBFs)
127:
+
-
LMH6553
V
+
V
-
22 pF
V
REF
127:
-
+
100:
100:
274:
274:
ADC14C105
14-Bit
105 MSPS
620 nH
620 nH
49.9:
68.1:
68.1:
0.1PF
+
-
V
CLAMP
50:
Single-Ended
AC-Coupled
Source
V
CM
LMH6553
www.ti.com SNOSB07H –SEPTEMBER 2008–REVISED MARCH 2013
DRIVING ANALOG TO DIGITAL CONVERTERS
Analog-to-digital converters present challenging load conditions. They typically have high impedance inputs with
large and often variable capacitive components. As well, there are usually current spikes associated with
switched capacitor or sample and hold circuits. Figure 63 shows the LMH6553 driving the ADC14C105. The
amplifier is configured to provide a gain of 2 V/V in a single-to-differential mode. The LMH6553 common mode
voltage is set by the ADC14C105. The 0.1 µF capacitor, in series with the 49.9Ω resistor, is inserted to ground
across the 68.1Ω resistor to balance the amplifier inputs. The circuit in Figure 63 has a 2nd order lowpass LC
filter formed by the 620 nH inductors along with the 22 pF capacitor across the differential inputs of the
ADC14C105. The filter has a pole frequency of about 50 MHz. The two 100Ω resistors serve to isolate the
capacitive loading of the ADC from the amplifier and ensure stability. For switched capacitor input ADCs, the
input capacitance will vary based on the clock cycle, as the ADC switches between the sample and hold mode.
See your particular ADC's datasheet for details.
Figure 63. Driving a 14-bit ADC
Figure 64 shows the SFDR and SNR performance vs. frequency for the LMH6553 and ADC14C105 combination
circuit with the ADC input signal level at −1 dBFS. The ADC14C105 is a single channel 14-bit ADC with
maximum sampling rate of 105 MSPS. The amplifier is configured to provide a gain of 2 V/V in single to
differential mode. An external bandpass filter is inserted in series between the input signal source and the
amplifier to reduce harmonics and noise from the signal generator. In order to properly match the input
impedance seen at the LMH6553 amplifier inputs, R
M
is chosen to match Z
S
|| R
T
for proper input balance.
Figure 64. LMH6553/ADC14C105 SFDR and SNR Performance vs. Frequency
The amplifier and ADC should be located as close together as possible. Both devices require that the filter
components be in close proximity to them. The amplifier needs to have minimal parasitic loading on it's outputs
and the ADC is sensitive to high frequency noise that may couple in on its inputs. Some high performance ADCs
have an input stage that has a bandwidth of several times its sample rate. The sampling process results in all
input signals presented to the input stage mixing down into the first Nyquist zone (DC to Fs/2).
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