Datasheet

127:
+
-
LMH6552
V
+
V
-
22 pF
V
REF
127:
-
+
100:
100:
274:
274:
ADC14DS105
14-Bit
105
MSPS
620 nH
620 nH
49.9:
68.1:
68.1:
0.1 PF
50:
Single-Ended
AC-coupled
Source
0
5 10 15 20 25 30
35 40
INPUT FREQUENCY (MHz)
50
55
60
65
70
75
80
85
90
(dB)
SFDR (dBc)
SNR (dBFs)
LMH6552
www.ti.com SNOSAX9H –APRIL 2007–REVISED MARCH 2013
Figure 51. LMH6552/ADC12DL080 SFDR and SNR Performance vs. Frequency
Figure 52 shows a combination circuit of the LMH6552 driving the ADC14DS105. The ADC14DS105 is a dual
channel 14-bit ADC with a sampling rate of 105 MSPS. The circuit in Figure 52 has a 2nd order low-pass LC
filter formed by the 620 nH inductor along with the 22 pF capacitor across the differential outputs of the
LMH6552. The filter has a pole frequency of about 50 MHz. Figure 53 shows the combined SFDR and SNR
performance over frequency with a −1 dBFs input signal and a sampling rate of 1000 MSPS.
Figure 52. Driving a 14-bit ADC
The amplifier is configured to provide a gain of 2 V/V in a single-to-differential mode. The LMH6552 common
mode voltage is set by the ADC14DS105. Circuit testing is the same as described for the LMH6552 and
ADC12DL080 combination circuit. The 0.1 µF capacitor, in series with the 49.9Ω resistor, is inserted to ground
across the 68.1Ω resistor to balance the amplifier inputs.
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