Datasheet

LMH6521

www.ti.com

SNOSB47D –MAY 2011–REVISED MARCH 2013

PIN DESCRIPTIONS

Pin Number Symbol Description

Analog I/O

30, 11 INA+, INB+ Amplifier non—inverting input. Internally biased to mid supply. Input voltage should not exceed

V+ or go below GND by more than 0.5V.

29, 12 INA−, INB− Amplifier inverting input. Internally biased to mid supply. Input voltage should not exceed V+ or

go below GND by more than 0.5V.

24, 17 OUTA+, OUTB+ Amplifier non—inverting output. Externally biased to 0V.

23, 18 OUTA−, OUTB− Amplifier inverting output. Externally biased to 0V.

Power

13, 15, 26, 28, GND Ground pins. Connect to low impedance ground plane. All pin voltages are specified with

center pad respect to the voltage on these pins. The exposed thermal pad is internally bonded to the

ground pins.

14, 27 +5V Power supply pins. Valid power supply range is 4.75V to 5.25V.

Common Control Pins

4, 5 MOD0, MOD1 Digital Mode control pins. These pins float to the logic hi state if left unconnected. See

Application Information for Mode settings.

22, 19 ENA, ENB Enable pins. Logic 1 = enabled state. See Application Information for operation in serial mode.

Digital Inputs Parallel Mode (MOD1 = 1, MOD0 = 1)

25, 16 A0, B0 Attenuation bit zero = 0.5dB step. Gain steps down from maximum gain (000000 = Maximum

Gain).

31, 10 A1, B1 Attenuation bit one = 1dB step.

32, 9 A2, B2 Attenuation bit two = 2dB step.

1, 8 A3, B3 Attenuation bit three = 4dB step.

2, 7 A4, B4 Attenuation bit four = 8dB step.

3, 6 A5, B5 Attenuation bit five = 16dB step.

21, 20 LATA, LATB Latch pins. Logic zero = active, logic 1 = latched. Gain will not change once latch is high.

Connect to ground if the latch function is not desired.

Digital Inputs Serial Mode (MOD1 =1, MOD0 = 0) SPI compatible

2 CLK Serial Clock

1 SDI Serial Data In. See Application Information for more details.

32 CSb Serial Chip Select (Active Low).

31 SDO Serial Data Out.

3, 4, 6, 7, 8, 9, 10, GND Pins unused in Serial Mode, connect to DC ground.

16, 20, 21, 25

Digital Inputs Pulse Mode (MOD1 = 0, MOD0 = 1)

2, 7 UPA, UPB Up pulse pin. A logic 0 pulse will increase gain one step.

1, 8 DNA, DNB Down pulse pin. A logic 0 pulse will decrease gain one step.

1 & 2 or 7 & 8 Pulsing both pins together will reset the gain to maximum gain.

31, 32 S0A, S1A Step size zero and step size 1. (0,0) = 0.5dB; (0, 1)= 1dB; (1,0) = 2dB, and (1, 1)= 6dB.

10, 9 S0B, S1B Step size zero and step size 1. (0,0) = 0.5dB; (0, 1)= 1dB; (1,0) = 2dB, and (1, 1)= 6dB.

3, 5, 6, 16, 25 GND Pins unused in Pulse Mode, connect to DC ground.

Product Folder Links: LMH6521