Datasheet

31 30 29 32
3
2
1
4
A3/SDI/DNA
A4/CLK/UPA
A5
MOD0
MOD1
B5
B4/UPB
B3/DNB
OUTA+
OUTA-
ENA
LATA
LATB
ENB
OUTB-
OUTB+
B2/S1B
B1/S0B
INB+
INB-
GND
+5V
GND
B0
A2/CS/S1A
A1/SDO/S0A
INA+
INA-
GND
+5V
GND
A0
27 26 25 28
7
6
5
8
10 11 12
9
14 15 16 13
22
23
24
21
18
19
20
17
GND
LMH6521
LMH6521
SNOSB47D –MAY 2011–REVISED MARCH 2013 www.ti.com
5V Electrical Characteristics
(1)
(continued)
The following specifications apply for single supply with V+ = 5V, Differential V
OUT
= 4V
PP
, R
L
= 200Ω, T
A
=25°C, f
in
= 200 MHz,
and Maximum Gain (0 attenuation). Boldface limits apply at temperature extremes.
Symbol Parameter Conditions Min
(2)
Typ
(3)
Max
(2)
Units
Power Requirements
VCC Supply Voltage 4.75 5.0 5.25 V
ICC Supply Current Both Channels Enabled 225 245 mA
ICC Disabled Supply Current Both Channels 35 mA
All Digital Inputs
Logic Compatibility TTL, 2.5V CMOS, 3.3V CMOS
VIL Logic Input Low Voltage 0.5 V
VIH Logic Input High Voltage 1.8 V
IIH Logic Input High Input Current Digital Input Voltage = 5V 200 μA
IIL Logic Input Low Input Current Digital Input Voltage = 0V –60 μA
Parallel and Pulse Mode Timing
t
GS
Setup Time 3 ns
t
GH
Hold Time 3 ns
t
LP
Latch Low Pulse Width 7 ns
t
PG
Pulse Gap between Pulses 20 ns
t
PW
Minimum Pulse Width Pulse Mode 15 ns
t
RW
Reset Width 10 ns
Serial Mode Timing and AC Characteristics
SPI Compatible
f
SCLK
Max Serial Clock Frequency 50 MHz
t
PH
SCLK High State Duty Cycle % of SCLK Period 50 %
t
PL
SCLK Low State Duty Cycle % of SCLK Period 50 %
t
SU
Serial Data In Setup Time 2 ns
t
H
Serial Data In Hold Time 2 ns
t
OZD
Serial Data Out TRI-STATE-to- Referenced to Negative edge of SCLK 10 ns
Driven Time
t
OD
Serial Data Out Output Delay Time Referenced to Negative edge of SCLK 10 ns
t
CSS
Serial Chip Select Setup Time Referenced to Positive edge of SCLK 5 ns
CONNECTION DIAGRAM
Figure 3. 32-Pin WQFN Package-Top View
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