Datasheet

t
CSH
1
st
clock
SCLK
8
th
clock
16
th
clock
CSb
t
CSS
t
CSH
t
CSS
t
ODZ
SDO
t
OZD
t
OD
D7 D0 D1
Clock out
Chip Select out
Data Out
Data In
Control Logic
LMH6521
CLK
CSb
SDI
SDO
V+ (Logic High)
Recommended:
R = 300 Ohms to 2000 Ohms
V+ (Logic) = 2.5V to 3.3V
For SDO (MISO) pin only:
V
OH
= V+,
V
OL
= (V+) ± [0.012*(R+20) + Vcesat]
R
20:
12 mA
Max
LMH6521
SNOSB47D –MAY 2011–REVISED MARCH 2013 www.ti.com
Figure 36. Serial Mode 4–wire Connection
Figure 37. Read Timing
Table 3. Read Timing
Data Output on SDO Pin
Parameter Description
t
CSH
Chip select hold time
t
CSS
Chip select setup time
t
OZD
Initial output data delay
t
ODZ
High impedance delay
t
OD
Output data delay
18 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMH6521