Datasheet

R
21
R
14
=
R
15
R
11
LMH6518
www.ti.com SNOSB21C –MAY 2008–REVISED JULY 2013
For a flat frequency response, the DC (low frequency) gain needs to be lowered to match the less-than-1 V/V AC
(high frequency) path gain through the JFETs. This can be done by increasing the value of R
2
.
By choosing the values of R
15
and R
11
so that
(19)
the frequency response at J10 Gate (and consequently the output) will remain flat when C
7
starts to conduct.
Offset correction is done by varying the voltage at R
4
, using a DAC or equivalent as shown, in order to shift the
LMH6518 +IN voltage relative to −IN. The result is a circuit which shifts the ground referenced scope input to
2.5V (V
CC
/2) CM with adjustable offset and without any JFET or BJT related offsets.
Note that the front-end attenuator (not shown) lower leg resistance should be increased for proper divider-ratio to
account for the 1 MΩ shunt due to the series combination of R
21
and R
14
. For example, a 10:1 front-end
attenuator could be formed by a series 900 kΩ and a shunt 111 kΩ for a scope BNC input impedance of 1 MΩ (=
900K + (111K || 1M)).
Table 8 lists other possible JFET candidates that fall in the range of speed (f
t
) and low noise needed:
Table 8. Suitable JFET Candidates Specifications
Company Part Number V
P
(V) I
dss
gm (mS) Input C noise
(1)
Break Calculated f
t
(mA) (pF) (nV/RtHz) down (V) (MHz)
Interfet IF140 −2.2 10 5.5 2.3 4 −20 380
Interfet IF142 −2.2 10 5.5 2.3 4 −25 380
Interfet 2N5397/8 −2.5 13 8 5 2.5 −25 254
Interfet 2N5911/2 −2.5 13 8 5 2.5 254
Interfet J308/9/10 −2.3 21 17 5.8 −25 466
Philips BF513 -3 15 10 5 318
Fairchild MMBF5486 −4 14 7 4 2.5 −25 278
Vishay
Siliconix SST441 −3.5 13 6 3.5 4 −35 272
(1) Noise data at ∼ I
dss
/2
The LNA noise could degrade the scope’s SNR if it is comparable to the input referred noise of the LMH6518.
LNA noise is influenced by the following operating conditions:
a. JFET equivalent input noise
b. BJT Base current
Reducing either “a” or “b” above, or both, reduces noise. One way to reduce “a” is to increase R
8
(currently set to
0Ω). This will reduce the noise impact of J8 but requires a JFET which has a higher I
dss
rating in order to
maintain the operating current of J10 so that J10’s noise contribution is minimized. Reducing the BJT Base
current can be accomplished with increasing R
20
at the expenses of higher rise/fall times. A higher β will also
reduce the Base current (keep in mind that β and f
t
at the operating Collector current is what matters).
Figure 70 shows the impact of the JFET buffer noise on SNR, compared to SNR in Figure 58, assuming either 3
nV/√Hz or 1.5 nV/√Hz buffer noise for comparison:
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