Datasheet

R
14
R
14
+ R
21
1 +
R
5
R
1
|| R
2
Gain (DC) =
¨
¨
©
§
¨
¨
©
§
#
1 V/V
Scope Input
Input Attenuators
Not Shown
C
6
5 pF
R
21
678 k:
R
14
322 k:
-
+
½ U1
LMV842
C
7
20 nF
C
3
100 nF
R
22
1 M:
R
15
678 k:
R
11
322 k:
LMH6518 +IN
Q0
BFQ67
J8
MMBF5486
R
20
500:
J10
MMBF5486
R
16
20:
-
+
½ U1
LMV842
-5V
+5V
LMH6518 -IN
+5V
R
5
500 k:
R
1
500 k:
R
3
500 k:
R
4
500 k:
R
0
500 k:
R
9
200:
R
6
200:
-10V
+10V
R
2
Adjust R
2
for gain matching
between DC and AC
C
0
1 nF
C
5
1 nF
R
17
100:
R
49
15:
R
50
15:
Offset Control
DAC
R
8
0:
LMH6518
SNOSB21C –MAY 2008–REVISED JULY 2013 www.ti.com
APPENDIX A
Here is the schematic drawing for a possible implementation of the LNA buffer shown in Figure 62:
Figure 69. JFET LNA Implementation
CIRCUIT OPERATION
This circuit uses an N-Channel JFET (J10) in Source-Follower configuration, to buffer the input signal, with J8
acting as a constant current source. This buffer presents a fixed input impedance (1 MΩ||10 pF) with a gain close
to 1 V/V.
The signal path is AC coupled through C
7
with DC (and low frequency) at LMH6518 +IN maintained through the
action of U1. NPN transistor Q0 is an emitter follower which isolates the buffer from the load (LMH6518 input and
board traces).
The undriven input of the LMH6518, −IN, is biased to 2.5V by R
6
, R
9
voltage divider. The Lower ½ of U1 inverts
this voltage and the upper ½ of U1 compares it to the combination of the driven output level at LMH6518 +IN and
the scaled version of scope input at R
14
, R
21
junction, and adjusts J10 Gate accordingly to set the LMH6518 +IN.
This control loop has a frequency response that covers DC to a few Hz, limited by the roll-off capacitor C
3
and
R
15
combination (1
st
order approximation). DC and low frequency gain is given by:
(18)
With the values in Figure 69 → R
2
≈ 452 kΩ:
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