Datasheet

Switch
>
J1
Oscilloscope
Input
900 k:
90 k:
10 k:
50:
LNA
FPGA
or
MPU
DAC
+IN
-IN
SPI
+OUT
-OUT
V
CM
+OUT Aux
-OUT Aux
V
CM_Aux
LMH6518
U1
Trigger
Circuit
+IN 1
-IN 1
V
CMO
Gsample/sec
8-Bit ADC
SPI (Full Scale
Voltage Control)
Attenuation = 100x
Channel 1
JFET Lo-Noise
Amp
Attenuation = 1x
Attenuation = 10x
Fine Gain Adjust
V
CC
Hi-Z/50:
Switch
Attenuator
Block
V
CC
200:
200:
1 nF
LMH6518
SNOSB21C –MAY 2008–REVISED JULY 2013 www.ti.com
Here is a block diagram for how the LMH6518 is used in an oscilloscope:
Figure 62. Digital Oscilloscope Front-End
From Figure 62, the signal path consists of the input impedance switch, the attenuator switch, Low Noise
Amplifier (LNA, JFET amplifier) to drive the LMH6518 input (+IN), and the DAC to provide offset adjust. The LNA
must have the following characteristics:
• Set U1’s common mode level to V
CC
/2 (∼2.5V)
• Very low drift (1 mV shift at LNA output could translate into 88 mV shift at LMH6518 output at max gain, or
∼13% of FS).
• Low output impedance (≤ 50Ω) to drive U1, for good settling behavior
• Low Noise (<0.98 nV/√Hz) to reduce the impact on the LMH6518 Noise Figure. Note that Figure 62 does not
show the necessary capacitors across the resistors in the front-end attenuators (see Figure 71). These
capacitors provide frequency response compensation and limit the noise contribution from the resistors so
that they do not impact the signal path noise. For more information about front-end attenuator design,
including frequency compensation, see REFERENCE for additional resources.
• Gain of 1 V/V (or very close to 1 V/V)
• Excellent frequency response flatness from DC to > 500-800 MHz to not impact the time domain performance
The undriven input (−IN) is biased to V
CC
/2 using a voltage driver. The impedance driving the LMH6518’s −IN
should be closely matched to the LNA’s output impedance for good settling time performance.
APPENDIX A shows one possible implementation of the LNA buffer along with performance data.
When the LMH6518’s Auxiliary output is not used, it is possible to disable this output using SPI-1 (see LOGIC
FUNCTIONS for SPI register map). Electrical Characteristics shows that by doing so, device power dissipation
decreases by the reduction in supply current of about 60 mA. As can be seen in Figure 63, in the absence of
heavy common loading, the Auxiliary output will be at a voltage close to 1.7V (V
CC
= 5V). With higher supply
voltages, the Auxiliary voltage will also increase and it is important to make sure any circuitry tied to this output is
capable of handling the 2.3V possible under V
CC
worst case condition of 5.5V.
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