Datasheet

31 30 29 32
3
2
1
4
A3/SDI/DNA
A4/CLK/UPA
A5
MOD0
MOD1
B5
B4/UPB
B3/DNB
OPA+
OPA-
ENA
LATA
LATB
ENB
OPB-
OPB+
B2/S1B B1/S0B
IPB+
IPB-
GND
+5V
GND
B0
A2/CS/S1A A1/SDO/S0A IPA+ IPA- GND +5V GND A0
27 26 25 28
7
6
5
8
10 11 12
9
14 15 16 13
22
23
24
21
18
19
20
17
GND
LMH6517
LMH6517
www.ti.com SNOSB19K –NOVEMBER 2008–REVISED MARCH 2013
CONNECTION DIAGRAM
Top View
Figure 1. 32-Pin WQFN Package
See Package Number RTV0032A
PIN DESCRIPTIONS
Pin Number Pin Name Description
Analog I/O
30, 11 IPA+, IPB+ Amplifier non—inverting input. Internally biased to mid supply. Input voltage should not exceed
V+ or go below GND by more than 0.5V.
29, 12 IPA−, IPB− Amplifier inverting input. Internally biased to mid supply. Input voltage should not exceed V+ or
go below GND by more than 0.5V.
24, 17 OPA+, OPB+ Amplifier non—inverting output. Internally biased to mid supply.
23, 18 OPA−, OPB− Amplifier inverting output. Internally biased to mid supply.
Power
13, 15, 26, 28, GND Ground pins. Connect to low impedance ground plane. All pin voltages are specified with
center pad respect to the voltage on these pins. The exposed thermal pad is internally bonded to the
ground pins.
14, 27 +5V Power supply pins. Valid power supply range is 4.5V to 5.25V.
Common Control Pins
4, 5 MOD0, MOD1 Digital Mode control pins. These pins float to the logic hi state if left unconnected. See below
for Mode settings.
22, 19 ENA, ENB Enable pins. Logic 1 = enabled state. See Application Information for operation in serial mode.
Digital Inputs Parallel Mode (MOD1 = 1, MOD0 = 1)
25, 16 A0, B0 Gain bit zero = 0.5dB step. Gain steps down from maximum gain (000000 = Maximum Gain)
31, 10 A1, B1 Gain bit one = 1dB step
32, 9 A2, B2 Gain bit two = 2dB step
1, 8 A3, B3 Gain bit three = 4dB step
2, 7 A4, B4 Gain bit four = 8dB step
3, 6 A5, B5 Gain bit five = 16dB step
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LMH6517