Datasheet

LMH6517
SNOSB19K –NOVEMBER 2008–REVISED MARCH 2013 www.ti.com
5V Electrical Characteristics
(1)
(continued)
The following specifications apply for single supply with V+ = 5V, Maximum Gain , R
L
= 100Ω, V
OUT
= 2 V
PP
, fin = 150 MHz.
Boldface limits apply at temperature extremes.
Parameter Test Conditions Min
(2)
Typ
(3)
Max
(2)
Units
Gain Step Phase Shift between any two steps 0.5 °
Gain Step Switching Time 15 ns
Power Requirements
ICC Supply Current Each channel (two channels per package) 80 91 mA
P Power Each Channel 400 mW
ICC Disabled Supply Current Each Channel 7.5 mA
All Digital Inputs
Logic Compatibility TTL, 2.5V CMOS, 3.3V CMOS
VIL Logic Input Low Voltage 0 0.4 V
VIH Logic Input High Voltage 2.0 3.6 V
IIH Logic Input High Input Current Digital Input Voltage = 3.3V −110 110 μA
IIL Logic Input Low Input Current Digital Input Voltage = 0V −110 110 μA
Parallel and Pulse Mode Timing
t
GS
Setup Time 3 ns
t
GH
Hold Time 3 ns
t
LP
Latch Low Pulse Width 7 ns
t
PG
Pulse Gap between Pulses 20 ns
t
PW
Minimum Latch Pulse Width 20 ns
t
RW
Reset Width 10 ns
Serial Mode Timing and AC Characteristics
SPI Compatible
f
SCLK
Serial Clock Frequency 10.5 MHz
t
PH
SCLK High State Duty Cycle % of SCLK Period 40 60 %
t
PL
SCLK Low State Duty cycle % of SCLK Period 40 60 %
t
SU
Serial Data In Setup Time 0.5 ns
t
H
Serial Data In Hold Time 5 ns
t
ODZ
Serial Data Out Driven-to- Tri-State Referenced to Positive edge of CS 40 50 ns
Time
t
OZD
Serial Data Out Tri-State-to-Driven Referenced to Negative edge of SCLK 15 20 ns
Time
t
OD
Serial Data Out Output Delay TIme Referenced to Negative edge of SCLK 15 20 ns
t
CSS
Serial Chip Select Setup TIme Referenced to Positive edge of SCLK 10 5
t
CSH
Serial Chip Select Hold TIme Referenced to Positive edge of SCLK 10 5
t
IAG
Inter-Access Gap Minimum time Serial Chip Select pin must 3 Cycles of
be asserted between accesses. SCLK
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