Datasheet
3
2
1
4
DNA
UPA
GND
GND
+3.3/NC
GND
UPB
DNB
OPA+
OPA-
ENA
GND
GND
ENB
OPB-
OPB+
S1B
S0B
IPB+
IPB-
GND
+5V
GND
GND
S1A
S0A
IPA+
IPA-
GND
+5V
GND
GND
7
6
5
8
22
23
24
21
18
19
20
17
GND
LMH6517
10
11
12
9
14
15
16
13
31
30
29
32
27
26
25
28
LMH6517
SNOSB19K –NOVEMBER 2008–REVISED MARCH 2013
www.ti.com
Table 3. Serial Word Format for LMH6517
C7 C6 C5 C4 C3 C2 C1 C0
1= read 0 0 0 0 0 0 0=Ch A
0=write 1=Ch B
Table 4. Serial Word Format for LMH6517 (cont)
Enable Gb5 Gb4 Gb3 Gb2 Gb1 Gb0 RES
1=On 1=+16dB 1=+8dB 1=+4dB 1=+2dB 1=+1dB 1=+0.5dB 0
0=Off
PULSE MODE (MOD1= 0, MOD0 = 1)
Pulse mode is a simple yet fast way to adjust gain settings. Using only two control lines per device the LMH6517
gain can be changed by simple up and down signals. Gain steps are selectable either by hard wiring the board
or using two additional logic inputs. For a system where gain changes can be stepped from one gain to the next
and where board space is limited this mode may be the best choice. The ENA and ENB pins are fully active
during pulse mode, and the channel gain state is preserved during the disabled state. See Typical Performance
Characteristics for disable and enable timing information.
Figure 55. Pin Functions for Pulse Mode
The LMH6517 supports a simple pulse up or pulse down control mode. In this mode the gain step size can be
selected from a choice of 0.5, 1, 2 or 6dB steps. In operation the gain can be quickly adjusted either up of down
one step at a time by a negative pulse on the UP or DN pins. This mode of operation is most suitable for
applications where board space is at a premium and high speed gain changes are desired. As shown in
Figure 56 each gain step pulse must have a logic high state of at least t
PW
= 20 ns and a logic low state of at
least t
PG
20 ns for the pulse to register as a gain change signal.
To provide a known gain state there is a reset feature in pulse mode. To reset the gain to maximum gain both
the UP and DN pins must be strobed low together as shown in Figure 56. There must be an overlap of at least
t
RW
= 20 ns for the reset to register.
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