Datasheet

SCLK
SCSb
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
R/Wb A3 A2 A1 A00 0 0
D7 D6 D5 D4 D3 D2 D1 D0C7 C6 C5 C4 C3 C2 C1 C0
Reserved (3-bits)
(MSB) (LSB)
COMMAND FIELD DATA FIELD
Address (4-bits)
Write DATA
SDI
SDO
Hi-Z
D7 D6 D5 D4 D3 D2 D1 D0
(MSB) (LSB)
Data (8-bits)
Read DATA
Single Access Cycle
Clock out
Chip Select out
Data Out
Data In
FPGA/DSP/uC/ASIC
LMH6517
CLK
CS
SDI (MOSI)
SDO (MISO)
V+ (Logic High)
Recommended:
R = 300 Ohms to 2000 Ohms
V+ (Logic) = 2.5V to 3.3V
For SDO (MISO) pin only:
V
OH
= V+,
V
OL
= (V+) - (R/(R+25)) * V+
R
25:
SDO
LMH6517
SNOSB19K –NOVEMBER 2008–REVISED MARCH 2013 www.ti.com
SDO: This is the data output pin. Ths SDO pin is an open drain output and requires an external bias resistor.
See Figure 51 for resistor sizing guidance. This output is normally at TRI-STATE and is driven only when SCSb
is asserted. Upon SCSb assertion, contents of the register addressed during the first byte are shifted out with the
second 8 SCLK falling edges. Upon power-up, the default register address is 00h.
Each serial interface access cycle is exactly 16 bits long as shown in Figure 52. Each signal's function is
described below. the read timing is shown in Figure 53, while the write timing is shown in figure Figure 54.
Figure 51. SDO Pin External Bias Resistor Configuration
Figure 52. Serial Interface Protocol (SPI compatible)
22 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMH6517