Datasheet

latcha
ga/gb[5:0]
cmode
V
SS
Pins: 9
MSPS: 62.5
Low Skew
FPGA/DSP/PC/ASIC
DVGA
latchb
pd
latcha
ga[5:0]
gb[5:0]
latchb
pd
6
ga[5:0]
gb[5:0]
cmode
V
SS
Pins: 13
MSPS: 333
High Skew
FPGA/DSP/P
C/ASIC
DVGA
pd
latcha
ga[5:0]
gb[5:0]
latchb
pd
6
6
V
SS
V
SS
LMH6517
SNOSB19K –NOVEMBER 2008–REVISED MARCH 2013 www.ti.com
Figure 48. Parallel Mode Connection Not Using Latch Pins (Latch pins tied to logic low state)
Figure 49. Parallel Mode Connection Using Latch Pins to Mulitplex Digital Data
SPI COMPATIBLE SERIAL INTERFACE (MOD1= 1, MOD0 = 0)
Serial interface allows a great deal of flexibility in gain programming and reduced board complexity. Using only 4
wires for both channels allows for significant board space savings. The trade off for this reduced board
complexity is slower response time in gain state changes. For systems where gain is changed only infrequently
or where only slow gain changes are required serial mode is the best choice.
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