Datasheet

www.ti.com Additional Design Tools
Near the power connector are a number of 0.1” pitch headers. The header labeled J1 provides off board
access to the LMH6517 digital control pins. The J1 pins and functions are described below. The jack
labeled J10 is normally loaded with a shorting jumper, it provides power to a 3.3V power supply used to
provide 3.3V logic signals to the digital pins. The jack labeled J11 is also loaded with a shorting block and
it provides the 5V power to the LMH6517. By removing the short on this jack and replacing it with an
ammeter the current drawn by the DVGA can be measured. The jack labeled J12 is a ground connector
and is normally left empty.
5 Additional Design Tools
The RD-179: High-IF Sub-sampling Receiver Subsystem board (SP16160CH1RB) is also available. This
reference design includes the ADC16DV160 ADC, the LMH6517 DVGA, and the LMK04031B precision
clock conditioner. Power regulation, filters and controlled impedance board layout are all provided in this
reference design. Please visit the TI website, www.ti.com for further details.
6 Gain Control
The LMH6517 DVGA has three control modes including, parallel mode, serial (SPI compatible) mode and
pulse mode. Parallel and pulse modes are fully supported on the board. Serial mode control requires the
use of a PC and the SPUSI2 USB to SPI interface board (available separately) or an external signal
source like a logic analyzer or a microcontroller. Each of the control modes is detailed fully below.
Mode SW1 Mode SW2 Gain Setting
(MOD1) (MOD0)
Off Off Parallel
Off On Serial
On Off Pulse
7 Parallel Mode
For ease of use, dip switches are provided to set the LMH6517 gain in parallel mode. This mode is the
easiest to use for basic measurements. To set the board in parallel mode, Dip-switch SW 1 which is
labeled MODE must be set such that the top switch is in the OFF position and the bottom switch is in the
OFF position (the top of the board is the Channel A portion). To move the MODE switches to the OFF
position, slide them toward the output SMA connectors.
In Parallel mode, the switch banks are used to set the gain of the DVGA. When using the DIP switches to
change gain in parallel mode ensure that the switch labeled LATA or LATB is in the ON position. With the
latch switch in the ON state the device is in transparent mode and any change in the dip switches is
immediately reflected in the device gain. Moving the latch pin switch to the OFF position holds the last
gain setting and ignores changes in the gain control switches. When the latch switch is in the OFF position
the dip switches that control the gain can be configured as desired and then implemented by momentarily
switching the LATA or LATB switch. For detailed instructions on the pin functions see Low Power, Low
Noise, IF and Baseband, Dual 16 bit ADC Driver With Digitally Controlled Gain Data Sheet (SNOSB19)
In parallel mode, the DIP switch banks SWGA and SWGB are used to set the gain of the DVGA. The gain
bits are binary weighted with the LSB representing a 0.5dB gain step and the MSB representing a 16dB
step. The steps increase the gain when the switch is in the ON position. For example, switching B5 from
OFF to ON will increase the gain by 16dB. Between the Gain control bits and the Latch switch is an
enable (ENA or ENB) switch. Setting this switch to the OFF position Enables the respective DVGA
channel.
8 Pulse Mode
The DVGA is also very easy to control in Pulse mode. For system implementations Pulse mode requires
fewer digital control lines than parallel mode at the expense of gain control speed. To use Pulse Mode the
Mode switches should be set such that MODE 1 is in the ON position and MODE2 is in the OFF position.
Gain changes are accomplished by using the UP and DN buttons. There are separate buttons for the A
channel and the B channel. Gain will be indicated on the LED displays.
5
SNOA553B–October 2010–Revised May 2013 AN-2081 LMH6517EVAL-R1 Evaluation Board
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated