Datasheet

-5V
100:
R
F1
1 k:
50:
R
1
100:
2 k:
LEVEL ADJ
R
G1
100:
2.2 µF
C
I
100 pF
2
3
1
6
7
4
LMH6504
2
3
1
6
7
4
LMH6504
25:
150:
OUTPUT
SIGNAL
INPUT
+5V
R
F2
1 k:
R
G2
100:
R
C
100:
R
B
R
2
U1
U2
LMH6504
SNOSA96D –NOVEMBER 2003–REVISED MARCH 2013 www.ti.com
Figure 50. Automatic Gain Control Circuit #2
CIRCUIT LAYOUT CONSIDERATIONS & EVALUATION BOARD
A good high frequency PCB layout including ground plane construction and power supply bypassing close to the
package are critical to achieving full performance. The amplifier is sensitive to stray capacitance to ground at the
I
-
input (pin 7); keep node trace area small. Shunt capacitance across the feedback resistor should not be used to
compensate for this effect. Capacitance to ground should be minimized by removing the ground plane from
under the body of R
G
. Parasitic or load capacitance directly on the output (pin 6) degrades phase margin leading
to frequency response peaking.
The LMH6504 is fully stable when driving a 100Ω load. With reduced load (e.g. 1k.) there is a possibility of
instability at very high frequencies beyond 400 MHz especially with a capacitive load. When the LMH6504 is
connected to a light load as such, it is recommended to add a snubber network to the output (e.g. 100Ω and 39
pF in series tied between the LMH6504 output and ground). C
L
can also be isolated from the output by placing a
small resistor in series with the output (pin 6).
Component parasitics also influence high frequency results. Therefore it is recommended to use metal film
resistors such as RN55D or leadless components such as surface mount devices. High profile sockets are not
recommended.
Texas Instruments suggests the following evaluation board as a guide for high frequency layout and as an aid in
device testing and characterization:
Device Package Evaluation Board
Part Number
LMH6504 SOIC CLC730066
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