Datasheet

LMH6503
www.ti.com SNOSA78E –OCTOBER 2003–REVISED APRIL 2013
Electrical Characteristics
(1)
(continued)
Unless otherwise specified, all limits ensured for T
J
= 25°C, V
S
= ±5V, A
V(MAX)
= 10, V
CM
= 0V, R
F
= 1kΩ, R
G
= 174Ω, V
IN_DIFF
= ±0.1V, R
L
= 100Ω, V
G
= +1V. Boldface limits apply at the temperature extremes.
Parameter Test Conditions Min
(2)
Typ
(2)
Max
(2)
Units
DC & Miscellaneous Performance
GACCU Gain Accuracy (see Application V
G
=1.0V +0.25 +0.9/−0.4
Information)
0V < V
G
< 1V ±0.3 +1.3/−1.5 dB
−0.7V < V
G
< 1V ±0.4 +4.4/−4.3
G Match Gain Matching (see Application V
G
= 1.0 – ±0.7
Information)
0 < V
G
< 1V – +1.7/−1.1 dB
−0.7V < V
G
< 1V – +4.0/−4.7
K Gain Multiplier (see Application 1.58 1.72 1.87
V/V
Information) 1.58 1.91
V
CM
Input Voltage Range Pin 3 & 6 Common Mode, ±2.0 ±2.2 V
|CMRR| > 50dB
(6)
±1.80
V
IN_ DIFF
Differential Input Voltage Across pins 3 & 6 ±0.34 ±0.37
V
±0.28
I
RG MAX
R
G
Current Pins 4 & 5 ±1.70 ±2.30 mA
±1.60
I
BIAS
Bias Current Pins 3 & 6
(7)
11 18
20
µA
Pins 3 & 6
(7)
, 3 10
V
S
= ±2.5V 13
TC
BIAS
Bias Current Drift Pin 3 & 6
(8)
100 nA/°C
I
OFF
Offset Current Pin 3 & 6 0.01 2.0
µA
2.5
TC I
OFF
Offset Current Drift See
(8)
5 nA/°C
R
IN
Input Resistance Pin 3 & 6 750 kΩ
C
IN
Input Capacitance Pin 3 & 6 5 pF
IV
G
V
G
Bias Current Pin 2, V
G
= 1.4V
(7)
45 µA
TC IV
G
V
G
Bias Drift Pin 2
(8)
20 nA/°C
R V
G
V
G
Input Resistance Pin 2 70 KΩ
C V
G
V
G
Input Capacitance Pin 2 1.3 pF
V
OUT
Output Voltage Range R
L
= 100Ω ±3.00 ±3.20
±2.97
V
R
L
Open ±3.95 ±4.05
±3.90
R
OUT
Output Impedance DC 0.1 Ω
I
OUT
Output Current V
OUT
±4V from Rails ±75 ±90 mA
±70
V
O OFFSET
Output Offset Voltage −1V < V
G
< 1V ±80 ±350 mV
±380
+PSRR +Power Supply Rejection Ratio Input Referred, 1V change, −80 −58 dB
(See
(9)
) V
G
= 1.4V −56
−PSRR −Power Supply Rejection Ratio Input Referred, 1V change, −67 −57 dB
(See
(9)
) V
G
= 1.4V −51
CMRR Common Mode Rejection Ratio Input Referred, V
G
= 1V −67 dB
(See
(10)
) −1.8V < V
CM
< 1.8V
(6) CMRR definition: [|ΔV
OUT
/ΔV
CM
|/A
V
] with 0.1V differential input voltage. ΔV
OUT
is the change in output voltage with offset shift
subtracted out.
(7) Positive current correspondes to current flowing in the device.
(8) Drift determined by dividing the change in parameter distribution at temperature extremes by the total temperature change.
(9) +PSRR definition: [|ΔV
OUT
/ΔV
+
| /A
V
], -PSRR definition: [|ΔV
OUT
/ΔV
−
| /A
V
] with 0.1V differential input voltage. ΔV
OUT
is the change in
output voltage with offset shift subtracted out.
(10) CMRR definition: [|ΔV
OUT
/ΔV
CM
|/A
V
] with 0.1V differential input voltage. ΔV
OUT
is the change in output voltage with offset shift
subtracted out.
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LMH6503