Datasheet

100
1k 10k 100k 1M
FREQUENCY (Hz)
10
100
1000
10000
eno (nV/
Hz)
MAX GAIN
MID GAIN
NO GAIN
A
VMAX
= 10
R
F
= 1k:
R
G
= 180:
V
RMS
= e
in
*
1.57 * (-3dB BANDWIDTH)
LMH6502
SNOSA65D –OCTOBER 2003–REVISED MARCH 2013 www.ti.com
(5)
Figure 60. Output Referred Voltage Noise vs. Frequency
CIRCUIT LAYOUT CONSIDERATIONS & EVALUATION BOARD
A good high frequency PCB layout including ground plane construction and power supply bypassing close to the
package are critical to achieving full performance. The amplifier is sensitive to stray capacitance to ground at the
I
−
input (pin 12); keep node trace area small. Shunt capacitance across the feedback resistor should not be used
to compensate for this effect. For best performance at low maximum gains (A
VMAX
< 10) +R
G
and -R
G
connections should be treated in a similar fashion. Capacitance to ground should be minimized by removing the
ground plane from under the body of R
G.
. Parasitic or load capacitance directly on the output (pin 10) degrades
phase margin leading to frequency response peaking.
The LMH6502 is fully stable when driving a 100Ω load. With reduced load (e.g. 1kΩ) there is a possibility of
instability at very high frequencies beyond 400MHz especially with a capacitive load. When the LMH6502 is
connected to a light load as such, it is recommended to add a snubber network to the output (e.g. 100Ω and
39pF in series tied between the LMH6502 output and ground). C
L
can also be isolated from the output by placing
a small resistor in series with the output (pin 10).
Component parasitics also influence high frequency results. Therefore it is recommended to use metal film
resistors such as RN55D or leadless components such as surface mount devices. High profile sockets are not
recommended.
Texas Instruments suggests the following evaluation boards as a guide for high frequency layout and as an aid in
device testing and characterization:
Device Package Evaluation Board Part Number
LMH6502MA SOIC LMH730033
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