Datasheet
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Configuration
2.2 Clock Buffer LMH2191
The oscillator frequency of the TCXO or any external input frequency is fed to the SCLK_IN pin of the
LMH2191 (DUT). The input of the DUT is AC coupled because of an internal coupling capacitor of around
30 pF. This means that any DC voltage added to the input frequency doesn't disturb the DUT from
functioning.
The DUT has two clock outputs which can be switched ON or OFF independently. When both outputs are
switched OFF the part is in shutdown mode and that means that the LDO is switched OFF too. In case the
TCXO is powered by the on board LDO of the DUT, the input frequency is switched OFF too. The current
consumption drops down to zero. ON and OFF switching of the outputs is performed by both CLK_REQ
inputs. Any of the clock outputs is OFF when the matching request input is low, thus connected to ground
or a voltage below 400 mV.
The testboard provides two jumpers J5 and J6 and the SMA edge launch connectors CON9 and CON10
connected to the CLK_REQ inputs, to switch the clock outputs ON or OFF. Each clock request input has
an internal pull down resistor of 200kΩ which means that when no jumper is placed the clock output is
OFF. To force a clock output to ON the voltage on the request pin must raise above 1.4V. The voltage
used to toggle the outputs ON or OFF is V
BAT
or an external voltage applied to the connectors CON9 and
CON10. If an external voltage is used, the jumpers for J5 and J6 must be removed. In default
configuration V
BAT
is used via the short on J5 and J6 to create a HIGH or LOW level for the CLK_REQ
inputs. In case there is a need to use an external voltage to create the HIGH or LOW level on the
CLK_REQ inputs this external voltage can be applied to J4 at the pins 3 and 4. Pin 3 is the ground
connection and pin 4 is the alternate voltage for V
BAT
.(NOTE: The jumper short for the pins 1 and 2 must
be removed then).
Both outputs are connected to an SMA edge launch connector (CON6 and CON7) and to the header
blocks J1 and J3. These headers are used to load the output with a specific capacitive load. There are
four capacitors that can be chosen to load the output. The lowest capacitor value is 10 pF and the highest
value is 47 pF. Using these capacitors each of the outputs can have a capacitive load varying from 10 pF
to 112 pF. When no jumper is placed on J1 or J3 the capacitive load is reduced to the capacity that arises
through the connected pcb tracks. When a cable connection is made at CON6 and CON7 be aware that
the capacitive load increases, and that due to insufficient termination and 50 ohm drive capability the
output signals can deteriorate.
2.2.1 Buffering the Clock Signals
To be able to connect the output signals and the TCXO signal to measuring equipment a high bandwidth
buffer (LMH6559) is included on the pcb. The output of this buffer is connected to an SMA edge launch
connector (CON8). This buffer is capable to drive a 50 ohm cable and load with a high magnitude. The
input of the buffer consists of a 6pin header block (J2) and has a pull down resistor of 100 kΩ to assure
the output is zero in case no jumper is placed on J2. Both CLK1 and CLK2 and the TCXO output signal
are connected to J2. By placing a jumper between pin 1 and 2 the CLK1 output signal is buffered and fed
to CON8. Placing the jumper between pin 3 and 4 connects the TCXO signal to CON8 and with the
jumper placed over the pins 5 and 6 the CLK2 signal is connected to CON8. The resistor R1, placed as a
series resistor in the output line, creates the possibility to use series termination in combination with the
connected cable and load. The default value for this resistor is zero ohm.
3 Configuration
The LMH2191 evaluation board can be configured via jumper settings. An overview of the various jumper
positions on the board is given in Figure 2. The settings of these jumpers and their functions are listed in
Table 1.
3
SNAA071A–July 2010–Revised May 2013 AN-2028 LMH2191 Evaluation Board
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