Datasheet

LMH1983
www.ti.com SNLS309G –APRIL 2010–REVISED JANUARY 2011
AUTO FORMAT DETECTION CODES
The Auto Format Detection Codes apply to registers 0x07 (Output Mode – PLL2 Format), 0x08 (Output Mode –
PLL3 Format) and 0x20 (Input Format).
Hsync Period Interlaced (I) /
Format Code Description
(in 27 MHz clocks) Progressive (P)
0 480i/29.97 1716 I
1 576I25 1728 I
2 480P59.94 858 P
3 576P50 864 P
4 720P60 600 P
5 720P59.94 600.6 P
6 720P50 720 P
7 720P30 1200 P
8 720P27.97 1201.2 P
9 720P25 1440 P
10 720P24 1500 P
11 720P23.98 1501.5 P
12 1080P60 400 P
13 1080P59.94 400.4 P
14 1080P50 480 P
15 1080P30 800 P
16 1080P29.97 800.8 P
17 1080P25 960 P
18 1080P24 1000 P
19 1080P23.98 1001 P
20 1080I30 800 I
21 1080I29.97 800.8 I
22 1080I25 960 I
23 1080I24 1000 I
24 1080I23.98 1001 I
25 48 kHz Audio 562.5 —
26 96 kHz Audio 281.25 —
27 44.1 kHz Audio 612.244898 —
28 32 kHz Audio 843.75 —
29 27 MHz Hsync 1 —
30 10 MHz Hysnc 2.7 —
31 User Defined User Defined User Defined
63 Unknown All Others
REGISTER DESCRIPTIONS
The following table provides details on the device's configuration registers. Default value for fields 7 bits and less
are expressed in binary, default values for fields that are 8 bits (Byte) are expressed in hex. Do not write to
Reserved (RSVD) fields.
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