Datasheet

LMH1983
SNLS309G –APRIL 2010–REVISED JANUARY 2011 www.ti.com
ELECTRICAL CHARACTERISTICS
(1)(2)
(continued)
Unless otherwise specified, all limits are specified for T
A
= 25°C, V
DD
= 3.3V, R
L_CLK
= 100Ω (CLKout differential load).
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min
(3)
Typ
(4)
Max
(3)
Units
Status Flag Outputs (NO_REF, NO_ALIGN,NO_LOCK)
V
OL
Low Output Voltage I
OUT
= +10 mA 0.4 V
V
OH
High Output Voltage I
OUT
= −10 mA V
DD
−0.4V V
Frame Timing Outputs
V
OL
Low Output Voltage I
OUT
=+10mA , Fout1, Fout2, Fout3
(5)
0.4 V
V
OH
High Output Voltage I
OUT
=-10mA Fout1, Fout2, Fout3
(5)
V
DD
-0.4V V
Output buffer shutdown, pin connected to V
DD
or GND
I
OZ
Output Shutdown Leakage Current 0.4 10 |µA|
V
DD
=3.465V
t
R
Rise Time 20% to 80% 15 pF Load 1 ns
t
F
Fall Time 20% to 80% 15 pF load 1 ns
TOF1 delay measured from the CLKout1 clock reset edge.
t
D1
(6)
Timing output delay time Delay spec applies for all output clock and format supported 22 ns
by the output pair following output initialization. 15 pF load.
TOF2 delay measured from the CLKout2 clock reset edge.
t
D2
Timing output delay time Delay spec applies for all output clock and format supported 2 ns
by the output pair following output initialization. 15 pF load.
TOF3 delay measured from the CLKout3 clock reset edge.
t
D3
Timing output delay time Delay spec applies for all output clock and format supported 2 ns
by the output pair following output initialization. 15 pF load.
TOF4 delay measured from the CLKout4 clock reset edge.
t
D4
Timing output delay time Delay spec applies for all output clock and format supported 22 ns
by the output pair following output initialization. 15 pF load.
Video and Audio Clock Outputs (CLKout1, CLKout2 and CLKout3)
Measured at CLKout1 all other CLKouts shutdown 250
27 MHz TIE deterministic Jitter fs
Measured at CLKout1, other CLKouts output default PLL 250
Measured at CLKout2 all other CLKouts shutdown 8
148.5 MHz TIE deterministic Jitter ps
Measured at CLKout2, other CLKouts output default PLL 8
t
DJ
Measured at CLKout3 all other CLKouts shutdown 4
148.35 MHz TIE deterministic Jitter ps
Measured at CLKout3, other CLKouts output default PLL 4
Measured at CLKout4 all other CLKouts shutdown 15
24.576 MHz TIE deterministic Jitter ps
Measured at CLKout4, other CLKouts output default PLL 15
Measured at CLKout1, other CLKouts shutdown 2.7
27 MHz TIE random Output Jitter
ps
(7)
Measured at CLKout1, other CLKouts output default PLL 2.7
Measured at CLKout2, other CLKouts shutdown 3.0
148.5 MHz TIE Random Output
ps
Jitter
(7)
Measured at CLKout2, other CLKouts output default PLL 3.0
t
RJ
Measured at CLKout3, other CLKouts shutdown 3.5
148.35 MHz TIE Random Output
ps
Jitter
(7)
Measured at CLKout3, other CLKouts output default PLL 3.5
Measured at CLKout4, other CLKouts shutdown 3.4
24.576 MHz TIE Random Output
ps
Jitter
(7)
Measured at CLKout4, other CLKouts output default PLL 3.4
T
D
Duty Cycle Measured at 50% level of clock amplitude, any output clock 50 %
Rise Time
t
R
15 pF load 400 ps
20% to 80%
Fall Time
t
F
15 pF load 400 ps
80% to 20%
V
OD
Differential Signal Output Voltage 100Ω differential load, CLKout1, CLKout2 or CLKout3
(8)
247 350 454 mV
(5) t
D
for FoutX is measured from the positive clock edge of CLKout to the negative edge of FoutX at the 50% levels
(6) t
D
for CLKoutX is measured from the positive clock edge of XOin to the positive clock edge of CLKoutX using 50% levels. The
measurement is taken at the clock cycle where the input and output clocks are phase aligned.
(7) The SD and HD clock output jitter is based on XO input clock with 20 ps peak-to-peak using a time interval error (TIE) jitter
measurement. The typical TIE peak-to-peak jitter was measured on the LMH1983 evaluation bench board using TDSJIT3 jitter analysis
software on a Tektronix DSA71604 oscilloscope and 1 GHz active differential probe. TDSJIT3 Clock TIE Measurement Setup: 10
-12
bit
error rate (BER), >100K samples recorded using multiple acquisitions Oscilloscope Setup: 20 mV/div vertical scale, 10 µs/div
horizontal scale, and 25 GS/s sampling rate
(8) The differential output swing and common mode voltage may be adjusted via the I
2
C interface. Testing is done with a value of 03Eh
loaded into register 0x3Ah
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