Datasheet

LMH1983
SNLS309G –APRIL 2010–REVISED JANUARY 2011 www.ti.com
PIN DESCRIPTIONS (continued)
Pin No. Pin Name I/O Signal Level Pin Description
12 NO_ALIGN O LVCMOS Loss of alignment status flag for OUTs 1–4 (active high)
13 NO_REF O LVCMOS Loss of reference status flag (active high)
14 CLKout4– O LVDS Audio clock from PLL4 (fundamental rate is 98.304 MHz).
15 CLKout4+ The output is 24.576 MHz by default and is selectable via the host.
16 VDD – Power 3.3V supply for CLKout4
17 Fout4 (OSCin) I/O LVCMOS Audio frame timing signal for OUT4 (active low.) Timing Generator fixed to PLL4
clock. The output is the audio-video-frame (AVF) pulse by default and is
programmable via the host. Optional OSCin function can be used to apply a 27
MHz external clock for PLL4 to generate an audio clock independent of the video
input reference; this function must be enabled via the host.
18 GND – GND Ground
19 VDD – Power 3.3V supply for PLL3 and PLL4
20 VDD – Power 3.3V supply for CLKout3
21 GND – GND Ground
22 Fout3 O LVCMOS Video frame timing signal for OUT3 (active low). Timing generator assignable to
PLL1, PLL2, or PLL3. OUT3 format is selectable via the host.
23 CLKout3+ O LVDS Video clock from PLL1, PLL2, or PLL3 depending on output crosspoint mode. The
24 CLKout3– output is 148.35 MHz by default and is selectable via the host.
25 Cbyp3 – Analog Bias bypass for on-chip LDO for PLL3
Connect to 1.0 uF and 0.1 uF bypass capacitors.
26 Cbyp4 – Analog Bias bypass for on-chip LDO for PLL4
Connect to 1.0 uF and 0.1 uF bypass capacitors.
27 Cbyp2 – Analog Bias bypass for on-chip LDO for PLL2
Connect to 1.0 uF and 0.1 uF bypass capacitors.
28 CLKout2+ O LVDS Video clock from PLL1, PLL2, or PLL3 depending on output crosspoint mode. The
29 CLKout2– output is 148.5 MHz by default and is selectable via the host.
30 Fout2 O LVCMOS Video frame timing signal for OUT2 (active low). Timing generator assignable to
PLL1, PLL2, or PLL3. OUT2 format is selectable via the host.
31 VDD – Power 3.3V supply for CLKout2
32 VDD – Power 3.3V supply for PLL2
33 XOin–
(3)
I LVCMOS/LV 27 MHz VCXO clock signal for PLL1.
34 XOin+ DS – LVCMOS: Directly connect clock signal to XOin+ and bias XOin- to mid-supply
with 0.1uF bypass capacitor.
– LVDS: Directly connect LVDS clock signals to XOin+ and XOin-.
Note: A TCXO or other clean 27 MHz oscillator can be applied for standalone
clock generation using PLLs 2-4 (bypass PLL1).
35 CLKout1– O LVDS Video clock from PLL1.
36 CLKout1+ The output is 27 MHz by default and is selectable via the host.
37 Fout1 O LVCMOS Reference frame timing signal for OUT1 (active Low). Timing generator fixed to
PLL1 OUT1 Format follows the reference input format.
38 VDD – Power 3.3V supply for CLKout1
39 GND – GND Ground
40 VC_LPF O Analog Loop filter for PLL1 charge pump output with VCXO Voltage Control (VC) sensing.
If free-run and holdover mode, PLL1 is disabled and an internal DAC outputs a
control voltage to the VCXO.
(3) XOin must be driven by a 27 MHz clock in order to read or write registers via I
2
C.
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