Datasheet

TCXO
27 MHz
±1ppm
LMH1983
27 MHz
148.5 MHz (PLL2)
148.35 MHz (PLL3)
98.304 MHz
A/V clock
signals will
track the TCXO
and have the
same accuracy
PLL1 Mode = Free run
PLL2 Video Format = 1080p/50
PLL3 Video Format = 1080p/59.94
PLL4 Audio Format = 98.304 MHz with 48 kHz word clock
CLKout1
CLKout4
CLKout2
CLKout3
Hin
Vin
Fin
No input
LOOP
FILTER
27 MHz
VCXO
LMH1983
Other clock inputs supported
32, 44.1, 48 or 96 kHz (Audio)
27 MHz (Video)
10 MHz (GPS)
27 MHz
74.25 MHz (PLL2)
74.176 MHz (PLL3)
98.304 MHz
A/V clock signals
genlocked to
clock ref. in
PLL1 Ref. In Format = Audio word, 27 MHz, or 10 MHz clock
PLL2 Video Format = 1080i/25
PLL3 Video Format = 1080i/29.97
PLL4 Audio Format = 98.304 MHz with 48 kHz word clock
CLKout1
CLKout4
CLKout2
CLKout3
Hin
LOOP
FILTER
27 MHz
VCXO
LMH1983
HD-SDI Upconverter
(HD/SD Simulcast)
with Audio Embedder
525i/29.97 SDI out
+ embedded audio
H blank
V blank
525i/29.97 digital
blanking pulse inputs
from FPGA SDI RX
F blank
27 MHz
148.5 MHz (PLL2)
148.35 MHz (PLL3)
24.576 MHz
525i/29.97 SDI in
+ embedded audio
A/V clock signals
genlocked to SDI in
1080i/29.97 SDI out
+ embedded audio
PLL1 Ref. In Format = 525i/29.97
PLL2 Video Format = 525i/29.97*
PLL3 Video Format = 1080i/29.97*
PLL4 Audio Format = 24.576 MHz with 48 kHz word clock
* GHQRWHV³3*&/.´PRGH(148.5 or 148.35 MHz)
CLKout1
CLKout4
CLKout2
CLKout3
Hin
Vin
Fin
LMH1983
SNLS309G APRIL 2010REVISED JANUARY 2011
www.ti.com
TYPICAL APPLICATION BLOCK DIAGRAMS
Three typical applications are shown below for the LMH1983 illustrating different input and output options.
Figure 23. 3G, 3G/1.001, and Audio Clock Generation for SD to HD SDI Upconversion with Audio
Embed/Disembed
Figure 24. A/V Clock Generation using a Recognized Clock-based Input Reference
Figure 25. High-Precision, Stable A/V Clock Generation using a 27 MHz TCXO Reference
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