Datasheet
4
3
2
1
6
5
V+
V-
U2
LMP7711MK
10.0k
R5
47 µF
CS
17.4k
RS
1 µF
CP
GND
GND
GND
18
GND
21
GND
39
DAP
41
VDD_PLL1
1
VDD_IO
2
VDD_IO
10
VDD_CLK4
16
VDD_PLL34
19
VDD_CLK3
20
VDD_CLK2
31
VDD_PLL2
32
VDD_CLK1
38
CLKout1+
36
CLKout1-
35
Fout1
37
CLKout2+
28
CLKout2-
29
Fout2
30
Fout3
22
CLKout3+
23
CLKout3-
24
CLKout4-
14
CLKout4+
15
Fout4/OSCin
17
Hin
3
Vin
4
Fin
5
INIT
6
ADDR
7
SDA
8
SCL
9
NO_LOCK
11
NO_ALIGN
12
NO_REF
13
Cbyp3
25
Cbyp4
26
Cbyp2
27
XOin-
33
XOin+
34
VC_LPF
40
U1
LMH1983SQ
Vdd3_3
Vdd3_3
0.1 µF
C12
GND
VC
1
OUT
4
GND
3
EN
2
VCC
6
OUTA
5
X1
357LB3I027M0000
49.9
R10
GND
CLK4_N
CLK4_P
Fout4
CLK3_N
CLK3_P
Fout3
CLK2_N
CLK2_P
Fout2
CLK1_N
CLK1_P
Fout1
0.1 µF
C7
0.1 µF
C4
0.1 µF
C2
1 µF
C1
1 µF
C3
1 µF
C6
GND
Vdd3_3
0.1 µF
C8
1 µF
C5
GND
VddCLK2
VddCLK3
VddCLK4
VddCLK1
VddPLL3
VddPLL2
VddPLL1
Hsync
Vsync
Fsync
INIT
SDA
SCL
0
R1
Do Not Load
0
R2
Do Not Load
GND
Vdd3_3
GND
VddVCXO
3.0k
R4
1.8k
R7
GND
Vdd3_3
NOREF
NOALIGN
NOLOCK
LMH1983
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SNLS309G –APRIL 2010–REVISED JANUARY 2011
TYPICAL INTERFACE CIRCUIT
A typical application circuit for the LMH1983 is shown in the Typical Interface Circuit. The key areas to consider
on this circuit are the loop filter – which consists of RS, CS, CP and the LM7711 Operational Amplifier which
buffers the loop filter output prior to driving the control voltage input of the VCXO. Care must be taken in the
component selection for the loop filter components (see the loop filter discussion above). The CLKout outputs are
differential, LVDS signals, and should be treated as differential signals. These signals may be laid out as fully
differential lines, in which the characteristic impedance between the two lines is nominally 100 Ω. Alternately,
loosely coupled lines may be used, in which case the characteristic impedance of each line should be 50 Ω
referenced to GND. In either case, care should be taken to match the lengths of the traces as closely as
possible. Trace length mismatches on a differential line will add to the jitter seen on that line. Jitter is also added
to the clock outputs if other signals are allowed to interfere with the signal traces, therefore, to the greatest extent
possibly, the clock traces should be isolated from other signals, especially avoiding long parallel runs. In places
where a hostile signal must cross a sensitive clock signal, it should be routed such that it crosses as closely as
possible to a 90° crossing.
Figure 22. LMH1983 Typical Interface Circuit
One potential source of jitter on a multiple clock system such as the LMH1983 is interference between the four
PLLs on the chip. To help reduce this effect, internally on the LMH1983 each PLL is run from a separate power
supply, and each supply has its own internal regulator. These regulators each require their own external bypass
as seen in the Typical Interface Circuit with bypass capacitors.
An I
2
C bus is also connected from the control system to the LMH1983. The LMH1983 will have one of three I
2
C
addresses, selected by the state of the ADDR pin, which may be tied high, tied low or left open. Depending on
the configuration of the control bus, it may require a pull-up resistor on the SDA and SCK pins.
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