Datasheet

LMH1983

SNLS309G –APRIL 2010–REVISED JANUARY 2011

www.ti.com

Figure 18. TOF1 Timing Figure 19. TOF2 Timing

Top Trace CLKout1, Bottom Trace TOF1 Top Trace CLKout2, Bottom Trace TOF2

10ns / div. Top 200mV / div, Bottom 1V / div 4ns / div, Top 200mV / div, Bottom 1V / div

Figure 20. TOF3 Timing Figure 21. TOF4 Timing

Top Trace CLKout3, Bottom Trace TOF3 Top Trace CLKout4, Bottom Trace TOF4

4ns / div, Top 200mV / div, Bottom 1V / div 10ns / div, Top 200mV / div, Bottom 1V / div

USER DEFINED FORMATS

There are several registers in the LMH1983 which are loaded automatically based on the format of the reference

that is detected. The LMH1983 allows the user to define a non-standard format, and the appropriate register

values to load into the registers if that format is detected. In order to identify the format, the LMH1983 measures

the frequency of the Hsync input, counts the number of lines per frame in the format, and detects if the particular

format is interlaced or progressive. The Hsync frequency is measured by counting the number of 27 MHz clock

edges occur in a period of time equal to 20 Horizontal sync times. To define the frequency the user must define a

minimum permissible count and a maximum count, thereby setting a window of frequency for Hsync. Registers

0x51 and 0x52 are used to define the 16 bit value for the low end of the frequency range, while registers 0x53

and 0x54 give the high end of the frequency range. Registers 0x5A and 0x5B are used to define the number of

lines per frame for the format, and bit 4 of register 0x5D is used to indicate if the user defined format is interlaced

or not. Finally bit 7 of 0x5D needs to be set in order to enable the detection of the user defined format. Once the

user defined format is detected, the contents of registers 0x55 through 0x59 are used to configure PLL1 to lock

to 27MHz, which is then used as the reference for PLL2, PLL3 and PLL4.

Product Folder Links: LMH1983