Datasheet
1
2
3
4
5
6
7
8
30
29
28
27
26
25
24
23
33
34
35
36
37
38
39
40
VDD
Vin
Fin
VC_LPF
CLKout3+
CLKout4-
XOin-
Cbyp2
VDD
Hin
NO_LOCK
INIT
Fout1
GND
NO_ALIGN
GND
Fout2
CLKout2+
SDA
CLKout3-
CLKout4+
9
SCL
10
22
21
Fout3
31
32
11
12
13
14
15
16
17
18
19
20
VDD
Fout4
(OSC in)
VDD
VDD
Cbyp3
CLKout2-
VDD
CLKout1-
CLKout1+
Die Attach Pad (DAP)
Connect to GND on PCB
ADDR
GND
Cbyp4
VDD
XOin+
VDD
VDD
NO_REF
LMH1983
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SNLS309G –APRIL 2010–REVISED JANUARY 2011
CONNECTION DIAGRAM
40-Pin WQFN (Top View)
Package Number RTA0040A
PIN DESCRIPTIONS
Pin No. Pin Name I/O Signal Level Pin Description
– DAP – GND Die Attach Pad (Connect to ground on PCB)
1 VDD – Power 3.3V supply for PLL1
2 VDD – Power 3.3V supply for logic I/O
3 Hin I LVCMOS Horizontal sync reference signal
Auto polarity correction for HVF will be based off Hin polarity.
Recognized clock inputs can be applied to Hin.
4 Vin I LVCMOS Vertical sync reference signal
5 Fin I LVCMOS Field sync (odd/even) reference signal
6 INIT I LVCMOS Reset signal for audio-video phase alignment (rising edge triggered)
7 ADDR I LVCMOS I
2
C address select
Pin settings:
– Tie low: 65h (7-bit slave address in hex)
– Float: 66h
– Tie high: 67h
8 SDA
(1)
I/O I
2
C I
2
C Data signal
9 SCL
(1)
I I
2
C I
2
C Clock signal
10 VDD – Power 3.3V supply for logic I/O
11 NO_LOCK
(2)
O LVCMOS Loss of lock status flag for PLLs 1-4 (active high)
(1) SDA and SCL pins each require a pull-up resistor of 4.7 kΩ to the VDD supply.
(2) The NO_LOCK status flag is derived from the Lock Status register bits (LOCK1-4) for each PLL. Each lock status bit can be masked
from the NO_LOCK flag by setting their respective mask bits.
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