Datasheet

÷ R PFD

Current

Source

÷ N VCO

CLK Out

27 MHz In

LMH1983

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SNLS309G –APRIL 2010–REVISED JANUARY 2011

The third mode is holdover mode. In the event that the reference is lost, there is an A/D — D/A pair which is able

to take over for the PLL control loop, and hold the VCXO control voltage constant. For this to work properly, the

device has to realize that it has lost its reference shortly after the reference is indeed lost. Some sync separators,

when the analog input is lost, will output random pulses from the H, V and F outputs, which can confuse the

device, therefore if holdover mode is to be used in conjunction with an analog sync separator, it is best to gate

the H, V, F signals with a signal which indicates if there is a valid reference input.

CONTROL of PLL2 and PLL3

PLL2 and PLL3 have the least amount of flexibility of the four PLLs in the LMH1983. They are pre-programmed

to run at 148.5 MHz and 148.35 MHz respectively. There is a ÷2 option available to allow the output to be 74.25

MHz or 74.18 MHz should these frequencies be required. The other controls available on these two PLLs are to

disable them – disabling PLL2 or PLL3 can save significant amounts of power if that particular clock is not

required.

Figure 7. PLL2 / PLL3 Block Diagram

CONTROL of PLL4

PLL4 is intended to generate a clock for audio use, but has a lot of versatility built into it. There is access to

several registers which may be used to configure PLL4 to generate any of a broad selection of frequencies. The

default state for PLL4 is to generate a 24.576 MHz (48 kHz x 512) on the output of CLK4, and a 5.996 Hz output

from TOF4. This is done by taking CLK1 (27 MHz), and dividing it by 75, resulting in a signal of 360 kHz, this is

compared to the internal PLL4 VCO, which is nominally 1.2 GHz, divided by 4096, which again yields 360 kHz.

This 1.2 GHz output is divided by 12 to generate a 98.304 MHz signal (48 kHz * 2048). Any power of two

multiple of 48 kHz can be generated by changing the contents of the PLL4_DIV component of register 0x34.

Note that the divider here is in powers of 2, so the default value of 2, results in the 98.304 MHz signal being

divided by 2

or 4. PLL4_DIV is a 4 bit value, so values up to 15 may be programmed, resulting in a divide by 2

or 32,768.

If audio clocks based on a 44.1 kHz sampling clock are desired, refer to applications note AN–2108 (SNLA129)

available on the TI web site for detailed instructions on how to set up the appropriate register settings to generate

44.1 kHz audio clocks.

TOF4 has two different modes in which it can operate. When the AFS_mode bit (in register 0x09) is set to a 0,

then TOF4 is derived by dividing down CLKout4 by a value of 2

TOF4_ACLK

(register 0x4A). if the AFS_mode bit is

set to a 1, then TOF4 is derived from TOF1 — divided by AFS_div (register 0x49). When AutoFormatDetect is

true, then the AFS_div register is read only, and is internally set depending upon the format detected.

Product Folder Links: LMH1983