Datasheet

NOLOCK
(output)
NOREF
(output)
reference
(input)
NOLOCK
(output)
NOREF
(output)
reference
(input)
Default SettingsFaster NOLOCK mode
LOCK ~ 4.4s
LOCK ~ 760 ms
LMH1983
SNLS309G –APRIL 2010–REVISED JANUARY 2011 www.ti.com
Separate from the time that it takes for the PLL to lock, there is a circuit which determines how to set the
NOLOCK output pin. The LMH1983 PLL operates by adjusting the voltage that is applied to the VCXO control
pin to lock the VCXO to a harmonic of the incoming reference. When the device is not locked, the PLL will be
pulling the VCXO control voltage to one extreme or the other of it’s range to slew the voltage into lock, once the
phase differences between the VCXO and the reference are small, the device begins to nudge the control
voltage one way or the other to maintain the phase difference. An adjustment might be necessary either because
of the VCXO drifting, or because of jitter on the reference.
Figure 6. Faster NOLOCK Reaction Mode timing
To determine the status of the NOLOCK indication, the LMH1983 sets up a window where it looks at the amount
of adjustment that is required, over a period of time. Each of these two parameters is set via a register – the
LOCK_STEP_SIZE register sets the amount of time to look at the signal over, and the LOCK_THRESHOLD
register sets the amount of variation in the control voltage that can be seen over this time frame while still
considering the device to be locked.
To minimize the amount of time that it takes to assert lock, load the LOCK_STEP_SIZE register (register #45,
0x2D ) with a value of 1, and the LOCK_THRESHOLD register (register #28, 0x1C) with a value of 31. The effect
of this can be seen in the 'Faster Reaction Mode timing diagram shown below.
VCXO SELECTION CRITERIA
The recommended VCXO is CTS part number 357LB3C027M0000 which has an absolute pull range of ±50 ppm
and a temperature range of –20°C to +70°C. A VCXO with a smaller APR can provide better frequency stability,
and slightly lower jitter, but the APR must be larger than the anticipated variation of the input frequency range.
FREE-RUN, LOCKED AND HOLDOVER MODES
The LMH1983 primary PLL can operate in three different modes, selected via register 0x05h. In Free-run mode,
H
IN
, V
IN
and F
IN
are not used, and the VCXO control voltage is set by the contents of registers 0x15 and 0x16.
By writing to these registers, the VCXO voltage can be trimmed up or down. the slave PLLs will remain locked to
the primary PLL.
In Genlock mode, the VCXO control voltage is actively controlled to maintain lock between H
IN
and the VCXO
output frequency. In addition there is a second loop which may take over to assert a lock between TOF1 and F
IN
.
See the section on TOF1 alignment for more details.
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