Datasheet

VC_LPF

LMH1983

www.ti.com

SNLS309G –APRIL 2010–REVISED JANUARY 2011

LOOP FILTER CAPACITORS

The most common types of capacitors used in many circuits today are ferroelectric ceramic capacitors such as

X7R, Y5V, X5R. Y5U, etc. These capacitors suffer from piezoelectric effects, which generate an electrical signal

in response to mechanical vibration, stress and shock. This effect can adversely affect the jitter performance

when presented to the control input to the VCXO. The easiest way to eliminate this effect is to use tantalum

capacitors which do not exhibit the piezoelectric effect.

Figure 5. External Loop Filter detail

LOCK DETERMINATION

There are four bits in register 2 that indicate the lock status of the four PLLs. Lock determination for PLL1 can be

controlled through two registers: LockStepSize (register 0x2D) and the Loss of Lock Threshold Register. The

LockStepSize register sets the amount of variation that is permitted on the VC_LPF pin while still considering the

device to be locked. If the reference to the LMH1983 has a lot of jitter on it, then the device may be reluctant to

declare lock if LockStepSize is set too low. The second register which controls the lock state declaration of PLL1

is Register 0x1C — Loss of Lock Threshold. This register sets a number of cycles on the H

input that must be

seen before loss of lock is declared. For some reference signals, there can be several missing H

pulses during

vertical refresh, so it is suggested that this register be loaded with a value greater than 6. Pin 11, NO_LOCK,

gives the lock status of the LMH1983. The status of the NO_LOCK pin can be read from register 0x01, and is a

logical OR of the four individual NO_LOCK status bits of the four PLLs, and is masked by the bits in the PLL

Lock mask (register 0x1D), and is also masked if an individual PLL is powered down.

LOCK TIME CONSIDERATIONS

The lock time of the LMH1983 is dominated by the lock time of PLL1. The other PLLs have much higher loop

bandwidths, and as a result lock much more quickly than does PLL1, therefore lock time considerations are all

focused on PLL1. The lock time for a PLL is dependent upon the loop bandwidth, the equation for which is listed

above in the PLL1 Loop Response Design Equations section. The LMH1983 also allows a 'Fastlock' mode, in

which the bandwidth is increased by increasing the charge pump current when the loop is unlocked, then at a

time programmed by the user after lock is declared, I

CP1

is throttled back to drop the bandwidth to the desired set

point. The result is both fast lock time and very low residual jitter.

Another issue to watch when considering lock time is if you have enabled 'drift lock' as described in the section

on TOF1 Alignment. If drift lock is enabled, and there is a significant difference in the phase of TOF1 relative to

the F

signal. In this case, the VCXO is slewed to ramp the clock rate up or down until the two framing signal are

brought into alignment. It is possible for this to take a long time (tens of seconds)

Product Folder Links: LMH1983