Datasheet

÷ R PFD
CP
Current
Source
÷ N
VCXO
(ext)
DAC
H in
SAR
MUX
÷ 1 or ÷ 2 CLK1 Out
PFD
V in
TOF1
Loop Filter
(ext)
LMH1983
SNLS309G –APRIL 2010–REVISED JANUARY 2011 www.ti.com
Under normal operation, several of these parameters are set by the device automatically, for example the charge
pump current and the value of 'FB_DIV'. When the input reference format changes, both N and the charge pump
current are updated, N is changed to allow for lock to the new reference, and the charge pump current is
adjusted to try to maintain constant loop bandwidth.
It should be noted that this bandwidth calculation is an approximation, and does not take into account the effects
of the damping factor or the second pole introduced by C
P
.
At frequencies far above the –3dB loop bandwidth the closed-loop frequency response of PLL1 will roll off at
about –40dB/decade, which is useful for attenuating input jitter at frequencies above the loop bandwidth. Near
the –3dB corner frequency, the roll-off characteristic will depend on other factors, such as damping factor and
filter order.
To prevent output jitter due to the modulation of the VCXO by the PLL's phase comparison frequency the
bandwidth needs to meet the following criterion:
• BW ≦(27 MHz / FB_DIV ) / 20
PLL1s damping factor can be approximated by:
• DF = (R
S
/2)√(I
CP1
*C
S
*K
VCO
/FB_DIV)
Where C
S
is the value of the series capacitor (in Farads)
Typically, DF is targeted to be between 1/√2 and 1 which will yield a good trade off between lock time and
reference spur attenuation. DF is related to the phase margin, which is a measure of the PLL stability.
There is a second parallel capacitor, C
P
which is needed to filter the reference spurs introduced by the PLL
which may modulate the VCXO control voltage, leading to jitter. The following relationship should be used to
determine C
P
:
• C
P
≈C
S
/20
The PLL loop gain, K can be calculated as:K = I
CP1
*K
VCO
/FB_DIV
Therefore Bandwidth and Damping Factor can be expressed in terms of K:
• BW = R
S
*K
• DF = (R
S
/2)*√(C
S
*K)
Figure 4. PLL1 Block Diagram
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