Datasheet

LMH1983
www.ti.com SNLS309G –APRIL 2010–REVISED JANUARY 2011
REFERENCE DETECTION
The default mode for the device is to use 'Auto Format Detect' in which the device determines the reference
format from among those shown in the Auto Format Detection Code table, and sets up the internal configurations
accordingly. There are 31 pre-defined formats, plus one format that the user can define which will be recognized.
The way that the device recognizes a format is by making a measurement of the H
IN
input frequency, and looking
at the V
IN
and F
IN
inputs, to determine if the reference input format is an interlaced or progressive input. For
some formats such as a 10 MHz or 27 MHz reference, if H
IN
and V
IN
are creating a spurious input, then the
device will not properly recognize the reference input and it will not lock properly to the reference. Because of
this, if H
IN
has one of these 'special' signals on it, V
IN
and F
IN
should be muted.
CONTROL OF PLL1
PLL1 generates a 27 MHz reference that is used as the primary frequency reference for all of the other PLLs in
the device. PLL1 has a dual loop architecture with the primary loop locking the external 27 MHz VCXO to a
harmonic of the H
IN
signal. In addition to this loop, there is a secondary loop which may be used in genlock
operations, this second loop compares the phase of the TOF1 output signal from the LMH1983 to the F
IN
signal.
This second loop may override the primary loop in order to bring the frame alignment of the output signals into
sync with the input reference. How to control this functionality is described in the section “TOF1 Alignment”
Since PLL2, PLL3 and PLL4 all have PLL1 as their input reference, the performance of PLL1 affects the
performance of all four clock outputs. The loop filters for the other three PLLs are all internal, and the bandwidths
are set significantly higher than that of PLL1, so all of the low frequency jitter characteristics of all four clock
outputs are determined by the loop response of PLL1. Accordingly, special attention should be paid the PLL1's
loop bandwidth and damping factor.
The loop response is primarily determined by the loop filter components and the loop gain. A passive second
order loop filter consisting of R
S
, C
S
and C
P
components can provide sufficient input jitter attenuation for most
applications. In some cases, a higher order filter may be used to further shape the low frequency response of
PLL1.
Several of these parameters are set by the device automatically, for example the charge pump current and the
value of 'N'. When the input reference format changes, both N and the charge pump current are updated, N is
changed to allow for lock to the new reference, and the charge pump current is adjusted to try to maintain
constant loop bandwidth.
The primary locking mechanism for PLL1 is to lock the 27 MHz output to a multiple of the H
IN
frequency, however
there is a second loop in which the phase of TOF1 and V
IN
are compared, and depending upon the mode of the
device, this loop can drive the VCXO control voltage to slew the output clocks into alignment.
PLL1 LOOP RESPONSE DESIGN EQUATIONS
The primary loop takes the reference applied to the H
IN
input, divides that by R (stored in registers 0x29 and
0x2A), and then compares it in phase and frequency to the output of the external VCXO divided by N (stored in
registers 0x2B and 0x2C) The PFD then generates output pulses which are integrated via an external loop filter
which drives the control voltage of the external VCXO (refer to PLL1 Block Diagram). Assuming a topology for
the loop filter which is similar to that shown in the PLL1 block diagram, the bandwidth of the PLL is determined
by:
BW
PLL1
= R
S
x K
VCO
x I
CP1
/FB_DIV
Where
• R
S
is the series resistor value in the external loop filter
• K
VCO
is the nominal 27 MHz VCXO gain in Hz/V. K
VCO
= Pull_range*27 MHz/Vin_Range. For the VCXO used
in the typical interface circuit (Mfgr: CTS, P/N 357LB3C027M0000): L
VCO
=100 ppm*27 MHz / (3.0V-0.3V) =
1000 Hz/V
• I
CP1
is the current from the PLL1 chargepump
• FB_DIV is the divide ratio of the PLL, which is set by the R and N register values, this will be equal to the
number of 27 MHz clock pulses in one H
IN
period. For NTSC this value will be 1716
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