Datasheet

SCL
SDA
D7 D6 D5 D4 D3 D2 D1 D0D7 D6 D5 D4 D3 D2 D1 D0
1 00110011 0 0
I
2
C
Slave
Address
$CD
Data Byte 1 Data Byte n
A
C
K
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
R
e
a
d
SCL
SDA
A7 A6 A5 A4 A3 A2 A1 A0
00110011 0
I
2
C
Slave
Address
$CC
Address
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
W
r
I
t
e
0
SCL
SDA
D7 D6 D5 D4 D3 D2 D1 D0A7 A6 A5 A4 A3 A2 A1 A0
0 00110011 0 0
I
2
C
Slave
Address
$CD
Address Data Byte n
A
C
K
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
R
e
a
d
D7 D6 D5 D4 D3 D2 D1 D0
0
Data Byte 1
A
C
K
LMH1983
SNLS309G –APRIL 2010–REVISED JANUARY 2011 www.ti.com
READ SEQUENCE
Read Sequences are made up of two I
2
C transfers. The first is the address access transfer, which consists of a
write sequence that transfers only the address to be accessed. The second is the data read transfer which starts
at the address indicated in the first transfer, and increments to the next address, continuing to read addresses
until a stop condition is encountered. The address access transfer is shown in the timing diagram below, it
consists of a start pulse, the slave device address including the read/write bit (a zero, indicating a write), and
then its ACK bit. The next byte is the address to be read, followed by the ACK bit, and the stop bit to indicate the
end of the address access transfer. The subsequent read data transfer shown consists of the start pulse, the
slave device address including the read/write bit (this time a ONE, indicating that the data is to be read) and the
ACK bit. The next byte is the data read from the initial access address. After each data byte read, the address is
incremented, so continuing to read from the device will provide the data in subsequent addresses. Each byte is
separated from the previous byte by an ACK bit, and the end of the read sequence is indicated with a STOP bit.
Figure 1. Write Sequence Timing diagram
Figure 2. Read Sequence — Address Access Transfer
Figure 3. Read Sequence — Data Read Transfer
INITIALIZATION
Under some circumstances, it is possible for an LMH1983 to power up in an anomalous state in which the output
of PLL3 exhibits a large amount of cycle to cycle jitter. A simple register write after power up will prevent the
device from remaining in this state. Writing to register 0x09 with a 0x02, and then writing to register 0x09 with a
0x00 insures that the device will not exhibit the poor duty cycle performance on CLKout3
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