Datasheet

LMH1983

SNLS309G –APRIL 2010–REVISED JANUARY 2011

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Table 3. Crosspoint Output Selection Table

(1)

PLL3_Disable

(1)

OUT2 Source OUT3 Source

0000 (default) 0 0 PLL2 PLL3

0001 1 1 PLL1 PLL1

0010 0 1 PLL2 PLL2

0011 1 0 PLL3 PLL3

0100 0 0 PLL3 PLL2

0101 1 0 PLL1 PLL3

0110 0 1 PLL2 PLL1

0111 0 1 PLL1 PLL2

1000 1 0 PLL3 PLL1

1001 Reserved Reserved Reserved Reserved

1010 Reserved Reserved Reserved Reserved

1011 Reserved Reserved Reserved Reserved

1100 Reserved Reserved Reserved Reserved

1101 Reserved Reserved Reserved Reserved

1110 Reserved Reserved Reserved Reserved

1111 Reserved Reserved Reserved Reserved

(1) PLL2_Disable and PLL3_Disable can be forced via register writes to the PLLx_DISABLE Registers independently of the status of the

Crosspoint Mode bits.

Table 4. Vsync Codes

Vsync Code

(1)

Frame Rate

Number (binary) Hz

0 (0000) 23.98 Hz

1 (0001) 24 Hz

2 (0010) 25 Hz

3 (0011) 29.97 Hz

4 (0100) 30 Hz

5 (0101) 50 Hz

6 (0110) 59.94 Hz

7 (0111) 60 Hz

(1) Vsync codes are used by registers 0x21(Output Frame Lookup –

Input Vsync Code), 0x22 (Output Frame Lookup – PLL2 Vsync

Code), and 0x23 (Output Frame Lookup – PLL3 Vsync Code)

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