Datasheet
LMH1983
SNLS309G –APRIL 2010–REVISED JANUARY 2011
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Table 2. Register Map (continued)
ADD Name Bits Field R/W Default Description
0x38 PLL4 Advanced Control 7:0 DIV_N4_LSB R/W 0x00 8 LSBs of the N divider in PLL4
N counter LSB
0x39 PLL4 Advanced Control 7:0 VCO4 Range R/W 0x16 The value in the VCO4 Range register is used to adjust the center
VCO Range frequency of PLL4.
0x3A LVDS Control 7 LVDS Boost R/W 0 Applies pre-emphasis to LVDS output
6:4 LVDS_DIFF R/W 100 Adjusts LVDS Differential output swing
3:0 LVDS_CM R/W 1001 Adjusts LVDS Common Mode output voltage
0x3B TOF1 Adv Control 7:5 RSVD Reserved
LPF MSB
4:0 TOF1_LPF_MSB R 00010 5 MSBs of the TOF1 lines per Frame count. This is read-only and
loaded automatically when Auto Format Detection is enabled
0x3C TOF1 Advanced Control 7:0 TOF1_LPF_LSB R 0x0D 8 LSBs of the TOF1 lines per Frame count. This is read-only and
LPF_LSB loaded automatically when Auto Format Detection is enabled
Together with register 0x3B this is a 13 bit number which number of
lines per frame. TOF1 will be at a frequency of Hsync divided by this
value.
0x3D TOF2 Advanced Control 7 RSVD Reserved
CPL MSB
6:0 TOF2_CPL_MSB R 000101 This 15 bit register gives the number of clock cycles per line to
0 calculate TOF2. It is loaded automatically based on the format set
with register 0x07.
0x3E TOF2 Advanced Control 7:0 TOF2_CPL_LSB R 0x50
CPL LSB
0x3F TOF2 Advanced Control 7:5 RSVD Reserved
LPF MSB
4:0 TOF2_LPF_MSB R 00010 This 13 bit register is loaded automatically based on the format
selected via register 0x07. It sets the number of lines per frame for
0x40 TOF2 Advanced Control 7:0 TOF2_LPF_LSB R 0x65
the selected format to set the TOF2 rate correctly.
LPF_LSB
0x41 TOF2 Advanced Control 7:5 RSVD Reserved
Frame Reset MSB
4:0 TOF2_RST_MSB R 00010 Automatically loaded based on formats selected.
0x42 TOF2 Advanced Control 7:0 TOF2_RST_LSB R 0x58
Frame Reset LSB
0x43 TOF3 Advanced Control 7 RSVD Reserved
CPL_MSB
6:0 TOF3_CPL_MSB R 000100 This 15 bit register gives the number of clock cycles per line to
0 calculate TOF3. It is loaded automatically based on the format set
with register 0x08.
0x44 TOF3 Advanced Control 7:0 TOF2_CPL_LSB R 0x98
CPL_LSB
0x45 TOF3 Advanced Control 7:5 RSVD Reserved
LPF_MSB
4:0 TOF3_LPF_MSB R 00100 This 13 bit register is loaded automatically based on the format
selected via register 0x08. It sets the number of lines per frame for
0x46 TOF3 Advanced Control 7:0 TOF3_LPF_LSB R 0x65
the selected format to set the TOF3 rate correctly.
LPF_LSB
0x47 TOF3 Advanced Control 7:5 RSVD Reserved
Frame Reset MSB
4:0 TOF3_RST_MSB R 00000 Automatically loaded based on formats selected.
0x48 TOF3 Advanced Control 7:0 TOF3_RST_LSB R 0x01
Frame Reset LSB
0x49 TOF4 Advanced Control 7:0 TOF4_AFS R/W 0x05 See Applications Information section for details. See also PLL4
AFS Block Diagram.
0x4A TOF4 Advanced Control 7:4 RSVD Reserved
ACLK
3:0 TOF4_ACLK R/W 1011 See Applications Information section for details. See also PLL4
Block Diagram.
0x4B Reserved 7:0 RSVD Reserved
to
0x50
0x51 User Auto Format 7:0 USR_27M_High_MSB R/W 0x00 User format detect is determined by looking at the frequency of the
27M High Value MSB Hsync input. This frequency is measured by counting the number of
27 MHz clock cycles that occur in 20 Hsync periods. This 16 bit
0x52 User Auto Format 7:0 USR_27M_High_LSB R/W 0x00
register lists the maximum number of 27 MHz clock cycles in 20
27M High Value LSB
Hsync periods that could be considered to meet the criteria for the
User Format
0x53 User Auto Format 7:0 USR_27M_Low_MSB R/W 0x00 User format detect is determined by looking at the frequency of the
27M Low Value MSB Hysnc input. This frequency is measured by counting the number of
27 MHz clock cycles that occur in 20 Hsync periods. This 16 bit
0x54 User Auto Format 7:0 USR_27M_Low_LSB R/W 0x00
register lists the minimum number of 27 MHz clock cycles in 20
27M Low Value LSB
Hsync periods that could be considered to meet the criteria for the
User Format
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