Datasheet
LMH1983
www.ti.com
SNLS309G –APRIL 2010–REVISED JANUARY 2011
Table 2. Register Map (continued)
ADD Name Bits Field R/W Default Description
0x26 PLL1 Advanced Control 7:4 RSVD Reserved
FastLock Delay
3:0 FastLock Delay R/W 0000 Sets the amount of time that PLL1_Lock must be asserted before
the PLL1 Charge pump current is reduced from the ICP1_Fast value
to the ICP1 value. The time delay is specified in units of half
seconds. Delay = FastlockDelay*0.5 Seconds. Valid values are from
0 to 10. Values from 11 to 15 are reserved.
0x27 PLL1 Advanced Control 4:0 FastLock Charge Pump R/W 11111 This field specifies the charge pump current to drive when FastLock
Fastlock CP Current Current is active. Charge pump current is equal to 34.375 µA * register
value
0x28 PLL1 Advanced Control 4:0 PLL1 Charge Pump R/W 01000 This field defines the charge pump current used when FastLock is
Charge Pump Current Current not active. Charge pump current is equal to 34.375 µA * register
value
0x29 PLL1 Advanced Control 7:2 RSVD Reserved
R Counter MSB
1:0 MSB R/W 00 The two LSBs of Register 0x29 along with the eight bits of Register
0x2A form a ten bit word which comprises the R divider for PLL1.
0x2A PLL1 Advanced Control 7:0 LSB R/W 0x01
This register is internally written based on the input format and when
R Counter LSB
AutoFormatDetect is enabled, these registers are read only.
0x2B PLL1 Advanced Control 7 RSVD Reserved
N Counter MSB
6:0 MSB R/W 000011 The 7 LSBs of Register 0x2B along with the eight bits of register
0 0x2C comprise the fifteen bit word which is used for the N divider of
PLL1. These registers are internally controlled based on the input
0x2C PLL1 Advanced Control 7:0 LSB R/W 0xB4
format detected and when AutoFormatDetect is enabled, these
N Counter LSB
registers are read only.
0x2D PLL1 Advanced Control 7:5 RSVD Reserved
Lock Step Size
4:0 Lock Step Size R/W 01000 See Applications section discussion on Lock Detect
0x2E PLL2 Advanced Control 7:5 RSVD Reserved
Main
4 PLL2_DIV R/W 0 0 = divide by 1
1 = divide by 2
3 PLL2_DISABLE R/W 0 0 = PLL2 disable is determined by XPT_MODE (Address 0x09)
1 = PLL2 is disabled
2:0 RSVD Reserved
0x2F PLL2 Advanced Control 7:4 RSVD Reserved
Charge Pump Current
3:0 ICP2 R/W 0010 Controls PLL2 Charge Pump Current
0x30 PLL2 Advanced Control 7:0 VCO_RNG2 R/W 0x0C Controls the VCO range
VCO Range
0x31 PLL3 Advanced Control 7:5 RSVD Reserved
Main
4 PLL3_DIV R/W 0 0 = divide by 1
1 = divide by 2
3 ICP3 R/W 0 0 = PLL3 disable is determined by XPT_MODE (Address 0x09)
1 = PLL3 is disabled
2:0 RSVD Reserved
0x32 PLL3 Advanced Control 7:4 RSVD Reserved
Charge Pump Current
3:0 ICP3 R/W 0011 Controls PLL3 Charge Pump Current
0x33 PLL3 Advanced Control 7:0 VCO_RNG3 R/W 0x05 Controls the VCO range
VCO Range
0x34 PLL4 Advanced Control 7:4 PLL4_DIV R/W 0010
Controls the PLL4 output divider — PLL4 is divided by 2
PLL4_DIV
Main
3 PLL4_Disable R/W 0 0 = PLL4 is enabled
1 = PLL4 is disabled
2 RSVD Reserved
1 IS125M R/W 0 0 = 100 MHz clock
1 = 125 MHz clock
0 PLL4_Mode R/W 0 0 = using 27 MHz Clock
1 = using external clock
0x35 PLL4 Advanced Control 7:4 RSVD Reserved
Charge Pump Current
3:0 ICP4 R/W 1000 Controls PLL4 Charge Pump Current
0x36 PLL4 Advanced Control 7 RSVD Reserved
R counter
6:0 DIV_R4 R/W 100101 Sets the R divider in PLL4
1
0x37 PLL4 Advanced Control 7:2 RSVD Reserved
N counter MSB
1:0 DIV_N4_MSB R/W 10 Two MSBs of the N divider in PLL4
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