Datasheet

LMH1983
SNLS309G –APRIL 2010–REVISED JANUARY 2011 www.ti.com
Table 2. Register Map (continued)
ADD Name Bits Field R/W Default Description
0x1C Loss of Lock Threshold 7:5 RSVD Reserved
4:0 LOCK1_Threshold R/W 10000 Sets the number of Hsync periods to wait before setting loss of lock.
Since during blanking there can have up to 5 missing Hsync pulses,
this value is usually set > 6.
0x1D Mask Control – PLL Lock 7 MASK_LOCK4 R/W 0 Setting this bit masks the PLL4 lock status in the global
and Output Align LOCK_STATUS bit.
6 MASK_LOCK3 R/W 0 Setting this bit masks the PLL3 lock status in the global
LOCK_STATUS bit.
5 MASK_LOCK2 R/W 0 Setting this bit masks the PLL2 lock status in the global
LOCK_STATUS bit.
4 MASK_LOCK1 R/W 0 Setting this bit masks the PLL1 lock status in the global
LOCK_STATUS bit.
3 MASK_TOF4_ALIGN R/W 0 Setting this bit masks the TOF4 align status in the global
ALIGN_STATUS bit.
2 MASK_TOF3_ALIGN R/W 0 Setting this bit masks the TOF3 align status in the global
ALIGN_STATUS bit.
1 MASK_TOF2_ALIGN R/W 0 Setting this bit masks the TOF2 align status in the global
ALIGN_STATUS bit.
0 MASK_TOF1_ALIGN R/W 0 Setting this bit masks the TOF1 align status in the global
ALIGN_STATUS bit.
0x1E Reserved 7:0 RSVD Reserved
0x1F Reserved 7:0 RSVD Reserved
0x20 Input Format 7:6 RSVD Reserved
5:0 Input Format 000000 When Auto Format Detection is enabled (EN_AFD, address 0x05),
this register is read-only and controlled automatically.
When Auto Format Detection is disabled, this register is writable via
I
2
C.
All writes to this register (whether automatic or manual) will update
all the LUT1 (Lookup Table 1), LUT2_2, and LUT2_3 output
registers based on the value written here. Writing to any of the
LUT1, LUT2_2, or LUT2_3 output registers will set this field to 6’d62
(0x3E) indicating that custom changes have been made.
0x21 Output Frame Lookup – 7:4 RSVD Reserved
Input Vsync Code
3:0 Input Vsync Code R/W 0011 Writes to this register update the Vsync code which tells the device
what the Input frame rate is. There is a table which correlates the
Vsync codes to the actual frame rates. When Auto Format Detection
is enabled (EN_AFD, address 5), this register is read-only, and is
automatically loaded by the device.
0x22 Output Frame Lookup – 7:4 RSVD Reserved
PLL2 Vsync Code
3:0 PLL2 Vsync Code R/W 0101 Whenever PLL2_FORMAT (address 7) is written, this field is
updated with the appropriate Vsync code. If any custom changes
are made the device will set this field to 4’d14 (0x0E) to so indicate.
0x23 Output Frame Lookup – 7:4 RSVD Reserved
PLL3 Vsync Code
3:0 PLL3 Vsync Code R/W 0110 Whenever PLL3_FORMAT (address 8) is written, this field is
updated with the appropriate Vsync code. If any custom changes
are made the device will set this field to 4’d14 (Ox0E) to so indicate.
0x24 Reserved 7:0 RSVD Reserved
0x25 PLL1 Advanced Control 7:5 RSVD Reserved
4 PLL1_DIV R/W 0 0 = Divide by 1 (Output is 27 MHz)
1 = Divide by 2 (Output is 13.5 MHz)
3 RSVD Reserved
2 PLL1 Input Mode R/W 0 Directly controls the mode of the PLL1 input buffer.
0 = Single Ended
1 = Differential
1 RSVD Reserved
0 FastLock 1 This bit enables ICP1_FAST (address 0x27) to be used during
locking.
0 = FastLock disabled
1 = FastLock enabled
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