Datasheet

LMH1983
www.ti.com SNLS309G –APRIL 2010–REVISED JANUARY 2011
Table 2. Register Map (continued)
ADD Name Bits Field R/W Default Description
0x14 Alignment Control – AFS 7:6 RSVD Reserved
5:4 AFS_Align_Mode R/W 11 00 = auto align when misaligned
01 = one shot manual align. AFS_Init_Input reg determines if done
by pin (INIT) or register (AFS_INIT = 1)
10 = always align
11= never align
3 AFS_Init_Input R/W 0 0 = Rising edges on INIT (pin 6) trigger AFS one shot manual align.
1 = Writing ‘1’ to AFS_Init register triggers AFS one shot manual
align.
2:1 RSVD Reserved
0 AFS_INIT R/W 0 Writing one to this bit while also writing AFS_Align_Mode = 3 and
AFS_Init_Input=1, or providing a rising edge on the init input when
AFS_Align_Mode ≠ 3 and AFS_Init_Input=0, will cause the
AFS_INIT output to go high for at least one vframe period + one
Hsync period and not more than one vframe period + two Hsync
periods. The assertion of AFS_INIT must happen immediately (it
cannot wait for Hsync). If AFS_Align_Mode = 3, toggling the init
input will have no effect.
This bit is self-clearing and will always read zero.
0x15 Loss of Alignment Control 7:3 RSVD Reserved
2:0 LOA_Window R/W 010 Number of 27 MHz clocks between the TOF1 and Vsync before
Loss of Alignment is reported.
If the code loaded in this register is n, then Loss of Alignment will be
reported if the difference between TOF1 and Vsync exceeds 2
n
27
MHz clock cycles
0x16 LOR Control – Holdover 7:2 RSVD Reserved
Sampled Voltage MSB
1:0 VC_Hold_MSB R 10 The VC_Hold[9:0] input signal changes rather slowly. For
synchronization, it should be sampled on consecutive 27 MHz
clocks until two identical values are found. This value will be saved
as VC_Hold_sampled[9:0].
Whenever the VC_Hold[9:8] register is read, VC_Hold_sampled[9:8]
is returned, and VC_Hold[7:0] will memorize the current value of
VC_Hold_sampled[7:0] (to be read at a later time).
This scheme allows a coherent 10-bit value to be read.
Returns a synchronized snapshot of the VC_Hold[9:8] (MSB).
0x17 LOR Control – Holdover 7:0 VC_Hold_LSB R NA The VC_Hold[9:0] input signal changes rather slowly. For
Sampled Voltage LSB synchronization, it should be sampled on consecutive 27 MHz
clocks until two identical values are found. This value will be saved
as VC_Hold_sampled[9:0].
Whenever the VC_Hold[9:8] register is read, VC_Hold_sampled[9:8]
is returned, and VC_Hold[7:0] will memorize the current value of
VC_Hold_sampled[7:0] (to be read at a later time).
This scheme allows a coherent 10-bit value to be read.
Returns a synchronized snapshot of the VC_Hold[7:0] (LSB)
0x18 LOR Control Free-run 7:2 RSVD Reserved
Control Voltage MSB
1:0 VC_Free_MSB R/W 01 Free-run Control Volage (VC_Free[9:0]) is the voltage asserted on
VC_LPF pin in free-run mode.
Writing will change the MSB (VC_Free[9:8])
0x19 LOR Control – Free-run 7:0 VC_Free_LSB R/W 0xFF Free-run Control Volage (VC_Free[9:0]) is the voltage asserted on
Control Voltage LSB VC_LPF pin in free-run mode.
Writing will change the LSB (VC_Free[7:0])
0x1A LOR Control – ADC & 7:2 RSVD Reserved
DAC Disable
1 ADC_Disable R/W 0 Directly controls the ADC_Disable output port.
0 = enable holdover ADC
1 = disable holdover ADC
0 DAC_Disable R/W 0 Directly controls the DAC_Disable output port.
0 = enable Free-run/Holdover DAC
1 = disable Free-run/Holdover DAC
0x1B Loss of Reference 7 RSVD Reserved
Threshold
6:4 HSYNC_Missing R/W 00 Sets the threshold for number of additional clocks to wait before
Threshold setting HSYNC_Missing.
3 RSVD Reserved
2:0 LOR_Threshold R/W 001 Sets the number of Hsync periods to wait before setting loss of
reference. Since during blanking there can have up to 5 missing
Hsync pulses, this value is usually set to 6.
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