Datasheet

LMH1983
SNLS309G –APRIL 2010–REVISED JANUARY 2011 www.ti.com
Table 2. Register Map (continued)
ADD Name Bits Field R/W Default Description
0X11 – CONTINUED
0x11 Alignment Control – TOF1 5:4 TOF1_Align_Mode R/W 11 00 = Auto-align when misaligned
01 = Reserved
10 = Always Align
11 = Never Align
NOTE: When H_ONLY is 1, TOF1 align mode is forced to never
align.
3 TOF1_Sync_Near R/W 1 This bit sets the PLL1/TOF1 output synchronization behavior when
the same reference is reapplied following a momentary LOR
condition and TOF1 is within 2 lines of the expected location.
0 = Drift Lock – ensures the outputs drift smoothly back to frame
alignment without excessive output phase disturbances
1 = Crash Lock – achieves the fastest frame alignment through
PLL/TOF counter resets, which can result in output phase
disturbances
2 TOF1_Sync_Far R/W 0 This bit sets the PLL1/TOF1 output synchronization behavior when
the same reference is reapplied following a momentary LOR
condition and TOF1 is within 2 lines of the expected location.
0 = Drift Lock – ensures the outputs drift smoothly back to frame
alignment without excessive output phase disturbances
1 = Crash Lock – achieves the fastest frame alignment through
PLL/TOF counter resets, which can result in output phase
disturbances
1 TOF1_Sync_Slew R/W 0 Sets the direction that TOF1 slews to achieve frame alignment when
a new reference is applied and TOF1 is outside of 2 lines of the
expected location.
0 = TOF1 lags by railing the VCXO input low
1 = TOF1 advances by railing the VCXO input high
0 RSVD Reserved
0x12 Alignment Control – TOF2 7:6 RSVD Reserved
5:4 TOF2_Align_Mode R/W 11 00 = auto align when misaligned
01 = one shot manual align when writing TOF2_INIT=1
10 = always align
11 = never align
3:1 RSVD Reserved
0 TOF2_INIT R/W 0 Writing one to this bit while also writing TOF2_Align_Mode = 3, will
cause the TOF2_INIT output to go high for at least one vframe
period + one Hsync period and not more than one vframe period +
two Hsync periods. The assertion of TOF2_INIT must happen
immediately (it cannot wait for Hsync). If TOF2_Align_Mode is being
written to 3, this bit will have no effect. This bit is self-clearing and
will always read zero.
0x13 Alignment Control – TOF3 7:6 RSVD Reserved
5:4 TOF3_Align_Mode R/W 11 00 = auto align when misaligned
01 = one shot manual align when writing TOF3_INIT=1
10 = always align
11= never align
3:1 RSVD Reserved
0 TOF3_INIT R/W 0 Writing one to this bit while also writing TOF3_Align_Mode ≠ 3, will
cause the TOF3_INIT output to go high for at least one vframe
period + one Hsync period and not more than one vframe period +
two Hsync periods. The assertion of TOF3_init must happen
immediately (it cannot wait for Hsync). If TOF3_Align_Mode is being
written to 3, this bit will have no effect. This bit is self-clearing and
will always read zero.
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