Datasheet

LMH1983
www.ti.com SNLS309G –APRIL 2010–REVISED JANUARY 2011
Table 2. Register Map (continued)
ADD Name Bits Field R/W Default Description
0x06 Input Polarity 7:4 RSVD Reserved
3 EN_AUTOPOL R/W 1 Enables Auto Polarity Detection and Correction. The proper polarity
needs to be set to synchronize the output timing signals to the
leading edges of the H and V inputs.
0 = The polarities of HVF inputs are manually set by their respective
polarity override registers.
1 = The polarity of the H input is auto-detected. The polarity
correction applied to the H input will also be applied to V and F
inputs.
2 HIN_POL_OVR R/W 0 Used to manually set the H input Polarity.
0 = Active Low (Negative polarity)
1 = Active High (Positive polarity)
1 VIN_POL_OVR R/W 0 Used to manually set the V input Polarity.
0 = Active Low (Negative polarity)
1 = Active High (Positive polarity)
0 FIN_POL_OVR R/W 0 Used to manually set the F input Polarity.
0 = Active Low (Negative polarity)
1 = Active High (Positive polarity)
0x07 Output Mode – PLL2 7:6 RSVD Reserved
Format
5:0 PLL2_Format R/W 001110 Sets the video format output timing for PLL2.
0x08 Output Mode – PLL3 7:6 RSVD Reserved
Format
5:0 PLL3_Format R/W 001101 Sets the video format output timing for PLL3.
0x09 Output Mode – Misc 7:5 RSVD Reserved
4 AFS Mode R/W 0 Sets the TOF4 output timing mode.
0 = Secondary Audio Clock Output (derived from PLL4 clock)
1 = Audio Frame Sync (derived from TOF1)
3:0 XPT_Mode R/W 0000 Sets the PLL/TOF crosspoint mode for Out2 and Out3.
Refer to the crosspoint output selection table.
0x0A Output Buffer Control 7:4 CLK_HIZ R/W 0000 [3] sets CLKout4 output buffer mode.
[2] sets CLKout3 output buffer mode.
[1] sets CLKout2 output buffer mode.
[0] sets CLKout1 output buffer mode.
0 = CLKoutx enabled
1 = CLKoutx Hi-Z
3:0 FOUT_HIZ R/W 1111 [3] sets Fout4 output buffer mode.
[2] sets Fout3 output buffer mode.
[1] sets Fout2 output buffer mode.
[0] sets Fout1 output buffer mode.
0 = Foutx enabled
1 = Foutx Hi-Z
0x0B Output Frame Control – 7:5 RSVD Reserved
Offset1_MSB
4:0 TOF1 Offset MSB R/W 00000 TOF1_Offset[12:0] sets number of lines to delay TOF1.
TOF1_Offset_MSB[4:0] sets TOF1_Offset[12:8]
0x0C Output Frame Control – 7:0 TOF1 Offset LSB R/W 0x00
TOF1_Offset_LSB[7:0] sets TOF1_Offset[7:0]
Offset1_LSB
0x0D Output Frame Control – 7:5 RSVD Reserved
Offset2_MSB
4:0 TOF2 Offset MSB R/W 00000 TOF2_Offset[12:0] sets number of lines to delay TOF2.
TOF2_Offset_MSB[4:0] sets TOF2_Offset[12:8]
0x0E Output Frame Control – 7:0 TOF2 Offset LSB R/W 0x00
TOF2_Offset_LSB[7:0] sets TOF2_Offset[7:0]
Offset2_LSB
0x0F Output Frame Control – 7:5 RSVD Reserved
Offset3_MSB
4:0 TOF3 Offset MSB R/W 00000 TOF3_Offset[12:0] sets number of lines to delay TOF3.
TOF3_Offset_MSB[4:0] sets TOF3_Offset[12:8]
0x10 Output Frame Control – 7:0 TOF3 Offset LSB R/W 0x00
TOF3_Offset_LSB[7:0] sets TOF3_Offset[7:0]
Offset3_LSB
0x11 Alignment Control – TOF1 7:6 RSVD Reserved
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