Datasheet

LMH1983
SNLS309G –APRIL 2010–REVISED JANUARY 2011 www.ti.com
Table 2. Register Map
ADD Name Bits Field R/W Default Description
0x00 Device Status 7 INTERLACED R — Indicates if the input reference format is an interlaced format
— Input Reference
6 ANALOG_REF R — This bit is set depending on if the sync detection circuit had
determined if the reference is an analog or digital derived signal
5 INPUT_POLARITY R — Returns the value of the input polarity determined by the sync
detector for HSYNC — 0 indicates an active low sync
4 HSYNC_STATUS R — This bit is set if the Hsync During Vsync detector will set
NO_H_DURING_V on the next rising edge of VSYNC
3 H_ONLY R — This is set by the Interlaced detector
2 LOR_STATUS R — Returns the inverse of the NO_REF output pin state
1 LOST_HSYNC R — Set if HSYNC_MISSING is high wile no_h_during_v is low. Remains
set until read, then self-clears
0 Reserved R — Reserved — always returns '0'
0x01 Device Status 7 Lock_Status R 1 Returns lock status for all unmasked and enabled PLLs
6 Align_Status R 0 Returns the Align Status for all enabled TOFs
5 Wrong_Format R 1 Returns the value of the Wrong_Format bit.
4 Holdover R 0 Returns the value of the PLL Holdover Bit
3:0 RSVD Reserved
0x02 PLL Lock and Output 7:4 Lock_Detect R – [7] indicates the lock status of PLL4.
Alignment Status [6] indicates the lock status of PLL3.
[5] indicates the lock status of PLL2.
[4] indicates the lock status of PLL1.
0 = PLL Not Locked
1 = PLL Locked
3:0 Align_Detect R – [3] indicates the lock status of TOF4.
[2] indicates the lock status of TOF3.
[1] indicates the lock status of TOF2.
[0] indicates the lock status of TOF1.
0 = TOF Alignment not detected
1 = TOF alignment detected
0x03 Revision ID 7:0 R 0xC0 Returns device revision code
0x04 Reserved 7:0 RSVD Reserved
0x05 Device Control 7 Soft_Reset R/W 0 Writing a ‘1’ will reset all registers to their default values. This bit is
self-clearing and always returns ‘0’ when read.
6 Powerdown R/W 0 Controls the power down function.
5 EN_AFD R/W 1 Enables Auto Format Detection (AFD).
0 = Auto Format Detect disabled
1 = Auto Format Detect enabled
4:3 PLL1_Mode R/W 01 Sets PLL1 operating mode:
00 = Force Free-run
01 = Genlock
10 = Force Holdover
11 = Reserved
2 LOR Mode R/W 0 Sets default mode of operation on Loss of Reference (LOR)
condition:
0 = Holdover on LOR
1 = Free-run on LOR
1 Force_148 R/W 1 When this bit is set, it forces the PLL2 and PLL3 clock rates to
148.xx MHz regardless of chosen output format. Otherwise, the
native clock rate of the chosen output format will be used.
0 = Uses the native clock rates
1 = Forces PLL2 = 148.5 MHz and PLL3 = 148.35 MHz clock rate
0 GOE R/W 1 Global Output Enable
0 = Disables all CLKout and Fout output buffers (Hi-Z)
1 = Enable active outputs
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