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Introduction

1.7 Free Run Control Voltage Input

The LMH1982 provides the option to set the VCXO's free run control voltage by external biasing of the

VC_FREERUN input (pin 1). The analog bias voltage applied to the VC_FREERUN input will be internally

connected to the LPF output (pin 31) though a low impedance switch when the LMH1982 is operating in

free run. The resultant voltage at the LPF output will drive the VCXO control input to set the free run

output frequency accuracy of the VCXO and LMH1982. The VC_FREERUN input should have low noise

and sufficient filtering to minimize VCXO input voltage modulation, which can result in excessive VCXO

and output clock jitter during free run operation.

The 50K potentiometer P1 can be adjusted to set the input voltage to VC_FREERUN between GND and

VDD. A LMP7701 (U8) op amp is used to buffer the voltage divider from P1. As an alternative to using P1,

an external voltage can be applied to header JP5 to set the VC_FREERUN voltage; however, you must

initially remove P1 and short R27.

1.8 Control Inputs

Switch SW1 allows the LMH1982 control inputs to be set to logic high (VDD) or logic low (GND). See

Table 6 for the toggle switch definitions for SW1.

Table 6. Control Input Switch, SW1

(1)

SWITCH LABEL LOW HIGH

REF_SEL Select REF_A Select REF_B

I2C_ENA Enable I

C Disable I

GENLOCK Genlock Mode Free Run Mode

RESET Reset operation Normal operation

(1)

The REF_SEL and GENLOCK inputs will only be functional after they have been enabled by programming the control registers.

During normal operation, the RESET input must be set high; otherwise the device will not function

properly. To reset the control registers of the LMH1982, toggle RESET low for at least 10 µs for proper

reset and then set high.

To enable programming via the I

C interface, the I2C_ENABLE input must be set low. If I2C_ENABLE is

set high and any attempt is made to communicate via I

C, the LMH1982 will not acknowledge, and

read/write operations will not occur.

The control inputs can be probed on the inside pins of header J9, while the edge-side pins of J9 are all

connected to GND. See Table 7 for the pin assignments of J9. If SW1 is removed, J9 may also be used to

apply external logic signals to the control inputs.

Table 7. Control Input Test Points, J9

Pin # Pin Name Pin # Pin Name

1 GND 8 REF_SEL

2 GND 7 I2C_ENABLE

3 GND 6 GENLOCK

4 GND 5 RESET

1.9 GENLOCK Status Indication

The evaluation board has two green LEDs (D3, D4) for visual indication of the PLL lock status and

reference status outputs, NO_LOCK and NO_REF. In Genlock mode, the PLL lock status is indicated by

D3 (labeled “GENLOCKED”) and the reference status is indicated by D4 (labeled “REFERENCE”). The

NO_LOCK and NO_REF outputs can be probed respectively at pins 7 and 8 of header J10.

Refer to the LMH1982 Multi-Rate Video Clock Generator with Genlock Data Sheet (SNLS289) for more

information about programming the PLL lock threshold and loss of reference threshold.

SNOA527A–May 2008–Revised April 2013 AN-1841 LMH1982 Evaluation Board

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