Datasheet

LMH1982
www.ti.com SNLS289C –APRIL 2008–REVISED MARCH 2013
Operating Ratings
V
DD
3.3V ± 5%
DV
DD
2.5V ± 5%
Input Voltage 0V to V
DD
Temperature Range, T
A
0°C to 70°C
Electrical Characteristics
Unless otherwise specified, all limits are specified for T
A
= 25°C, V
DD
= 3.3V, DV
DD
= 2.5V, Boldface limits apply at the
temperature extremes.
Parameter Test Conditions Min
(1)
Typ
(2)
Max
(1)
Units
I
VDD
V
DD
Supply Current Default register settings, no input 47 mA
reference, 27 MHz VCXO and loop filter
I
DVDD
DV
DD
Supply Current 39 mA
connected, 100Ω differential load on
SD_CLK and HD_CLK outputs; no load
on all other outputs
I
VDD
V
DD
Supply Current V
DD
= 3.465V, DV
DD
= 2.75V, Genlock 57 70 mA
mode, 1080p/59 output timing, HD_CLK
I
DVDD
DV
DD
Supply Current 44 60 mA
= 148.35 MHz, SD_CLK = 67.5 MHz,
100Ω differential load on SD_CLK and
HD_CLK outputs; no load on all other
outputs
Free Run Voltage Control Input (Pin 1)
V
IL
Low Analog Input Voltage
(3)
0 V
V
IH
High Analog Input Voltage
(3)
V
DD
V
Reference Inputs (Pins 4, 5, 7, 8)
V
IL
Low Input Voltage I
IN
= ±10 μA 0 0.3 V
DD
V
V
IH
High Input Voltage I
IN
= ±10 µA 0.7 V
DD
V
DD
V
ΔT
HV
H-V Sync Timing Offset Input timing offset measured from H 2.0 μs
sync to V sync pulse leading edges
(4)
Digital Control Inputs (Pins 6, 13, 14, 15)
V
IL
Low Input Voltage I
IN
= ±10 µA 0 0.3 V
DD
V
V
IH
High Input Voltage I
IN
= ±10 µA 0.7 V
DD
V
DD
V
I
2
C Interface (Pins 11, 12)
V
IL
Low Input Voltage 0 0.3 V
DD
V
V
IH
High Input Voltage 0.7 V
DD
V
DD
V
I
IN
Input Current V
IN
between 0.1 V
DD
and 0.9 V
DD
−10 +10 μA
I
OL
Low Output Sink Current V
OL
= 0V or 0.4V 3 mA
Status Flag Outputs (Pin 16, 17)
V
OL
Low Output Voltage I
OUT
= +10 mA 0.4 V
V
OH
High Output Voltage I
OUT
= −10 mA V
DD
−0.4V V
Top of Frame Output (Pin 25)
V
OL
Low Output Voltage I
OUT
= +10 mA 0.4 V
V
OH
High Output Voltage I
OUT
= −10 mA V
DD
−0.4V V
I
OZ
Output Hi-Z Leakage TOF output in Hi-Z mode, output pin 0.4 10 |μA|
Current connected to V
DD
or GND
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(3) The input voltage to VC_FREERUN (pin 1) should also be within the input range of the external VCXO. The input voltage should be
clean from noise that may significantly modulate the VCXO control voltage and consequently produce output jitter during free run
operation.
(4) ΔT
HV
is a required specification that allows for proper frame decoding and subsequent output initialization (alignment). For interlace
formats, the H-V sync timing offset must be within ΔT
HV
for all even fields and be outside ΔT
HV
for odd fields. For progressive formats,
the H-V sync timing offset must be within ΔT
HV
for all frames. See sections Reference Frame Decoder and Output Frame Line Offset.
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